SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 6

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TMP1940
8.
9.
10.
11.
7.6
7.7
7.8
7.9
7.10
7.11
8.1
8.2
8.3
9.1
9.2
9.3
10.1
10.2
10.3
10.4
10.5
10.6
11.1
11.2
8.1.1
8.1.2
8.2.1
8.2.2
8.2.3
8.2.4
8.3.1
8.3.2
8.3.3
9.1.1
9.1.2
10.2.1
10.2.2
10.2.3
10.3.1
10.3.2
10.3.3
10.3.4
10.3.5
10.3.6
10.3.7
10.3.8
10.4.1
10.4.2
10.4.3
10.4.4
10.4.5
10.4.6
10.4.7
10.5.1
External Bus Interface........................................................................................................................................... 72
Chip Select/Wait Controller .................................................................................................................................. 81
DMA Controller (DMAC)..................................................................................................................................... 90
8-Bit Timers (TMRAs)........................................................................................................................................ 115
Port 5 (P50–P57) ............................................................................................................................................. 53
Port 7 (P70–P77) ............................................................................................................................................. 54
Port 8 (P80–P87) ............................................................................................................................................. 58
Port 9 (P90–P97) ............................................................................................................................................. 61
Port A (PA0–PA7) ........................................................................................................................................... 66
Open-Drain Output Control ............................................................................................................................. 71
Address and Data Buses .................................................................................................................................. 73
External Bus Operation.................................................................................................................................... 74
Bus Arbitration ................................................................................................................................................ 79
Programming Chip Select Ranges ................................................................................................................... 81
Chip Select/Wait Control Registers ................................................................................................................. 87
Application Example ....................................................................................................................................... 89
Features............................................................................................................................................................ 90
Implementation ................................................................................................................................................ 91
Register Description ........................................................................................................................................ 93
Operation ....................................................................................................................................................... 103
DMA Transfer Timing ................................................................................................................................... 112
Programming Example .................................................................................................................................. 114
Block Diagrams ............................................................................................................................................. 116
Timer Components ........................................................................................................................................ 118
Supported Configurations ....................................................................................................................... 73
States of the Address Bus During On-Chip Address Accesses ............................................................... 73
Basic Bus Operation ............................................................................................................................... 74
Wait Timing ............................................................................................................................................ 75
ALE Pulse Width .................................................................................................................................... 77
Read Recovery Time............................................................................................................................... 78
Bus Access Control................................................................................................................................. 79
Bus Arbitration Flow .............................................................................................................................. 79
Relinquishing the bus.............................................................................................................................. 80
Base/Mask Address Registers (BMA0–BMA3) ..................................................................................... 81
Base Address and Address Mask Value Calculations ............................................................................. 84
On-Chip DMAC Interface....................................................................................................................... 91
DMAC Block.......................................................................................................................................... 92
Bus Snooping.......................................................................................................................................... 92
DMA Control Register (DCR) ................................................................................................................ 94
Channel Control Registers (CCRn)......................................................................................................... 95
Channel Status Registers (CSRn)............................................................................................................ 97
Source Address Registers (SARn) .......................................................................................................... 98
Destination Address Registers (DARn) .................................................................................................. 99
Byte Count Registers (BCRn) ............................................................................................................... 100
DMA Transfer Control Registers (DTCRn).......................................................................................... 101
Data Holding Register (DHR)............................................................................................................... 102
Overview............................................................................................................................................... 103
Transfer Request Generation................................................................................................................. 106
DMA Address Modes ........................................................................................................................... 107
DMA Channel Operation ...................................................................................................................... 108
DMA Channel Priority.......................................................................................................................... 110
Interrupts............................................................................................................................................... 110
Data Packing and Unpacking ................................................................................................................ 111
Dual-Address Mode .............................................................................................................................. 112
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