SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 114

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.
External Bus Interface
internal busses and the memory or peripherals in the external address space. It consists of the External Bus
Interface (EBIF) logic and the Chip Select/Wait Controller.
select function supports automatic wait-state generation and data bus sizing (8-bit or 16-bit) for each of the four
address blocks and the rest of the external address locations.
EBIF logic also performs dynamic bus sizing and bus arbitration.
(1) Wait-state generation
(2) Data bus width
(3) Read recovery cycles
(4) ALE pulse width
(5) Bus arbitration
The TMP1940CYAF contains external bus interface logic that handles the transfer of information between the
The CS/Wait Controller provides four programmable chip select signals, with variable block sizes. The chip
The EBIF logic controls the timing of the external bus, based on the settings of the CS/Wait Controller. The
cycles inserted between two consecutive external bus cycles.
Selectable ALE pulse width (0.5 or 1.5 cycles). This setting applies to all the address blocks.
Individually programmable for each address block
Individually programmable (8-bit or 16-bit) for each address block
Individually programmable (to up to 2 cycles) for each address block. Read recovery cycles are dummy
Automatic insertion of up to seven wait cycles
WAIT pin
TMP1940CYAF-72
TMP1940CYAF