SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 136

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Note 1: When the snoop request is disabled (CCRn.SReq=0), a software reset of the DMAC must be performed in the
Note 2: If the software reset command is written to the DCR register immediately after the completion of the last transfer
Note 3: Don’t issue a software reset command to the DCR register via a DMA transfer.
Rst
31
W
15
Bits
31
10.3.1
30
following sequence:
Execute steps 3 and 4 consecutively.
cycle of a DMA transaction, the DMA-done interrupt will not be cleared. In this case, the software reset only
initializes channel registers, etc.
Mnemonic
1. Disable interrupts.
2. Execute NOP four times.
3. Perform a software reset.
4. Perform a software reset again.
5. Re-enable interrupts.
DMA Control Register (DCR)
Rst
Reset
Field Name
Figure 10.3 DMA Control Register (DCR)
Performs a software reset of the DMAC. When the Rst bit is set to 1, all the DMAC
internal registers are initialized to their reset values. Any transfer requests are
removed and all the four DMA channels are put in Idle state.
0: Don’t-care
1: Resets the DMAC.
TMP1940CYAF-94
0
0
Description
TMP1940CYAF
16
0
: Read/Write
: Read/Write