SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 154

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.5 DMA Transfer Timing
10.5.1
All DMAC operations are synchronous to the rising edges of the internal system clock.
A[23:16]
AD[15:0]
CS
RD
CS
WR
Dual-Address Mode
0
1
Memory-to-memory transfer
size programmed to 16 bits. A block of data is transferred until the BCRn register reaches 0.
Memory-to-I/O transfer
transfer size programmed to 16 bits.
Figure 10.14 shows a DMA cycle from one external 16-bit memory to another, with the transfer
Figure 10.15 shows a DMA cycle from a 16-bit memory to an 8-bit I/O peripheral, with the
A[23:16]
AD [15:0]
Figure 10.14 Memory-to-Memory Transfer (Dual-Address Mode)
CS
RD
CS
WR / HWR
Figure 10.15 Memory-to-I/O Transfer (Dual-Address Mode)
0
1
tsys
tsys
Addr
TMP1940CYAF-112
Read
Data
Addr
Read
Data
Addr
Write
Addr
Data
Write
Data
Addr
Write
Data
TMP1940CYAF