SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 182

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Note 1: The prescaler's output clock Tn must be selected so that the relationship Tn < fsys/2 is satisfied.
Note 2: Do not change the clock gear value while the timer is running.
Note 3: The — character means “Don’t use.”
12.2 Timer Components
SYSCR1.FPSEL
Peripheral Clock
12.2.1
0 (gear)
Select
1 (fc)
Prescaler
prescalar clock source ( T0) can be selected from fperiph, fperiph/2 and fperiph/4 by programming the
PRCK[1:0] field of the SYSCR0 located within the CG. fperiph can be selected from fgear (geared
clock) and fc (non-geared clock) by programming the FPSEL bit of the SYSCR1 located within the CG.
A write of 1 to this bit starts the prescalar. A write of 0 to this bit clears and halts the prescalar.
12.2 shows prescalar output clock resolutions (@fc = 32 MHz).
The TMRB0 has a 5-bit prescalar that slows the rate of a clocking source to the counter. The
The TB0RUN bit in the TB0RUN register allows the enabling and disabling of the TMRB0 prescalar.
Prescalar output taps can be divide-by-2 ( T1), divide-by-8 ( T4) and divide-by-32 ( T16). Table
SYSCR1.GEAR[1:0]
Clock Gear Value
01 (fc/2)
10 (fc/4)
11 (fc/8)
01 (fc/2)
10 (fc/4)
11 (fc/8)
Table 12.2 Prescaler Output Clock Resolutions
00 (fc)
00 (fc)
TMP1940CYAF-140
SYSCR0.PRCK[1:0]
Prescaler Clock
00 (fperiph/4)
01 (fperiph/2)
10 (fperiph)
00 (fperiph/4)
01 (fperiph/2)
10 (fperiph)
00 (fperiph/4)
01 (fperiph/2)
10 (fperiph)
00 (fperiph/4)
01 (fperiph/2)
10 (fperiph)
00 (fperiph/4)
01 (fperiph/2)
10 (fperiph)
00 (fperiph/4)
01 (fperiph/2)
10 (fperiph)
00 (fperiph/4)
01 (fperiph/2)
10 (fperiph)
00 (fperiph/4)
01 (fperiph/2)
10 (fperiph)
Source
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
Prescaler Output Clock Resolution
2
2
3
3
3
3
(0.125 s)
4
5
4
6
5
(0.125 s)
(0.25 s)
(0.25 s)
(0.25 s)
(0.25 s)
(1.0 s)
(0.5 s)
(1.0 s)
(0.5 s)
(2.0 s)
T1
TMP1940CYAF
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
3
3
3
5
4
6
5
4
7
6
5
8
7
6
5
4
5
4
5
4
5
(0.25 s)
(0.25 s)
(0.25 s)
(1.0 s)
(0.5 s)
(2.0 s)
(1.0 s)
(0.5 s)
(4.0 s)
(2.0 s)
(1.0 s)
(8.0 s)
(4.0 s)
(2.0 s)
(1.0 s)
(0.5 s)
(1.0 s)
(0.5 s)
(1.0 s)
(0.5 s)
(1.0 s)
T4
@fc = 32 MHz
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
10
7
6
5
8
7
6
8
7
8
7
6
5
7
6
5
7
6
5
7
6
5
9
9
T16
(4.0 s)
(2.0 s)
(1.0 s)
(8.0 s)
(4.0 s)
(2.0 s)
(8.0 s)
(4.0 s)
(8.0 s)
(4.0 s)
(2.0 s)
(1.0 s)
(4.0 s)
(2.0 s)
(1.0 s)
(4.0 s)
(2.0 s)
(1.0 s)
(4.0 s)
(2.0 s)
(1.0 s)
(16 s)
(16 s)
(32 s)