SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 139

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Act
31
15
R
0
Bit
2:0
31
23
22
21
20
19
18
10.3.3
30
Mnemonic
BED
Conf
AbC
BES
Channel Status Registers (CSRn)
Act
NC
Channel Active
Normal
Completion
Abnormal
Completion
Reserved
Source Bus Error
Destination Bus
Error
Configuration
Error
Reserved
Field Name
0
Figure 10.5 Channel Status Registers (CSRn)
Reset value = 0
Indicates whether or not the DMA channel is in Ready state.
1: The DMA channel is in Ready state.
0: The DMA channel is not in Ready state.
Reset value = 0
If set, the DMA channel has terminated by normal completion. If the NIEn bit in the
CCRn is set, an interrupt is generated. The NC bit is cleared by writing a 0 to it.
Clearing the NC bit causes the interrupt to be cleared.
The NC bit must be cleared prior to starting the next transfer. An attempt to set the Str
bit in the CCRn when NC=1 will cause an error.
A write of 1 has no effect on this bit.
1: The DMA channel has terminated by normal completion.
0: The DMA channel has not terminated by normal completion.
Reset value = 0
If set, the DMA channel has terminated with an error. If the AbIEn bit in the CCRn is
set, an interrupt is generated. The AbC bit is cleared by writing a 0 to it. Clearing the
AbC bit causes the interrupt to be cleared.
The AbC bit must be cleared prior to starting the next transfer. An attempt to set the
Str bit in the CCRn when AbC=1 will cause an error.
A write of 1 has no effect on this bit.
1: The DMA channel has terminated with an error.
0: The DMA channel has not terminated with an error.
This bit is reserved and must be written as 0.
Reset value = 0
1: A bus error has occurred during the source read cycle.
0: A bus error has not occurred during the source read cycle.
Reset value = 0
1: A bus error has occurred during the destination write cycle.
0: A bus error has not occurred during the destination write cycle.
Reset value = 0
1: A configuration error is present.
0: No configuration error is present.
These bits are reserved and must be written as 0s.
0
TMP1940CYAF-97
24
R/W
NC
23
0
AbC
R/W
22
0
R/W
21
0
Description
BES
20
R
0
SED
19
R
0
3
TMP1940CYAF
Conf
18
R
0
2
R/W
17
00
00
16
0
: Reset Value
: Read/Write
: Read/Write
: Reset Value