SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 370

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.3
3.3.1
Operating Modes
unused.
Single Boot mode and Programmer mode. Of these modes, User Boot mode and Single Boot mode are
collectively referred to as on-board programming modes.
is soldered on a printed circuit board. In Single Boot mode, new data comes from a serial port under control
of a Toshiba-provided routine in the boot ROM. User Boot mode allows you to create an algorithm of your
own for flash memory erase and program operations.
memory while in Programmer mode. This security feature can be enabled upon completion of on-board
programming to reduce the potential risk of software leaks to third parties.
determine the mode of operation for the flash memory, as shown in Table 3.2. After
(
When Programmer mode is selected,
remain stable once the flash memory is put in a given mode of operation.
Note 1: Don’t care. The pins must be held at 1 or 0, however.
Note 2: Hold P40 at logic 1, and P41 and P42 at logic 0. 3.7.3 Pin Functions and Settings for a description
Single-Chip Mode
Single Boot Mode
Programmer Mode
BOOT
Operating Mode
(1)
(2)
(3)
(4)
The TMP1940FDBF offers a total of five operating modes, including the one in which the flash memory is
The on-chip flash memory can be re-programmed in one of the following three modes: User Boot mode,
On-board programming modes allow for re-programming of the flash memory while the TMP1940FDBF
The TMP1940FDBF flash memory provides a security feature to prevent intrusive access to the flash
The logic states on the BW0, BW1,
After a reset, the CPU operates in compliance with the selected mode, except for Programmer mode.
#
Overview
Normal Mode
User Boot Mode
Single-Chip Mode (Interleave)
Single-Chip Mode (Single-Clock)
Single Boot Mode
Programmer Mode (Note 2)
) and P86 (INTLV) can be configured as either general-purpose I/O pins or timer output pins.
of how other pins must be maintained in Programmer mode.
After a reset, the TX19 core processor executes out of the on-chip flash memory. Either fast (one-
clock) or interleave mode operation is selected through the INTLV (P86) pin when
released.
Single-Chip mode is further divided into Normal mode in which the user application executes and
User Boot mode which allows for re-programming of the flash memory while the TMP1940FDBF is
installed on a printed circuit board.
The user can freely define how to switch between Normal mode and User Boot mode. For
example, the logic state on, say, Port 00, can be used to determine whether to put the flash
memory in Normal mode or User Boot mode. The user must include a routine in the application
program to test the state of that port.
After a reset, the TX19 core processor executes out of the on-chip boot ROM (which is a mask
ROM). The boot ROM contains a routine to aid users in performing on-board programming of the
flash memory via a serial port of the TMP1940FDBF. The serial port is connected to an external
host which transfers new data according to a prescribed protocol.
This mode allows for re-programming of the flash memory with a general-purpose EPROM
programmer. Use the programmer and programming adaptor recommended by Toshiba.
Operating Mode
Table 3.2 Modes of Operation
Table 3.1 Operating Modes
TMP1940FDBF-12
RESET
BOOT
must be held at logic 0. The input pins listed in Table 3.2 must
(P85) and INTLV (P86) pins during a reset sequence
RESET
0
0
0
Description
0
1
1
1
BW0
1
1
1
0
Input Pins
BW1
TMP1940FDBF
1
1
1
1
RESET
RESET
Note 1
1
1
0
is released, P85
RESET
INTLV
Note 1
Note 1
1
0
is