SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 172

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

dynamically by writing a new value into the register buffer. Upon a match between the TA1REG and
the UC0, the TA0REG latches a new value from the register buffer.
square wave with virtually any (and variable) duty cycle.
In 8-bit PPG mode, if the double-buffering function is enabled, the TA0REG value can be changed
The TA0REG can be loaded with a new value upon every match, thus making it easy to generate a
Example: Generating a 50-kHz square wave with a 25% duty cycle (fc = 32 MHz)
X = Don’t care,
TA0REG (compare value)
TA01RUN
TA01MOD
TA0REG
TA1REG
TA1FFCR
P7CR
P7FC
TA01RUN
Match Between TA0REG
Match Between TA1REG
follows:
A 50-kHz waveform has a period of 20 µs. Under the above clocking conditions, T1 has a 0.25-
µs resolution (@fc = 32 MHz). When T1 is used as the timer clock source, the TA1REG should
be loaded with:
TA0REG should be loaded with:
Clocking conditions:
The time constant values to be loaded into the TA0REG and TA1REG are determined as
With a 25% duty cycle, the high pulse width is calculated as 20 µs
System clock:
High-speed clock gear: ×1 (fc)
Prescaler clock:
20 s
5 s
and Up-Counter 0
and Up-Counter
Register Buffer
MSB
0.25 s
0.25 s
– = No change
20 s
7
0
1
0
0
X
1
Figure 11.14 Register Buffer Operation
6
X
0
0
1
X
X
20 (14H)
5
X
X
0
0
X
X
80 (50H)
TMP1940CYAF-130
4
X
X
1
1
X
X
High-speed (fc)
fperiph/4 (fperiph = fsys)
(Up-Counter
3
X
0
0
0
2
0
X
1
0
1
1
Q
1
1
0
0
0
0
1
1
1
1
LSB
0
0
1
0
0
X
1
Q
1
Q
)
2
Stops and clears the TMRA0.
Selects 8-bit PPG mode and T1 as the clock
source.
Writes 14H.
Writes 50H.
Sets the TA1FF to 1 and enables toggling.
If these bits are set to 10, a low-going pulse is
generated.
Configures P71 as the TA1OUT output pin.
Starts the TMRA0 and the TMRA1.
(Up-Counter
Shift-Trigger for Register Buffer
TMP1940CYAF
Q
2
)
Q
2
Write to TA0REG
(Register Buffer).
1/4 = 5 µs. Thus, the
Q
3