SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 248

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.5.4
14.5.5
(2) Clock Synchronization
Slave Addressing and Address Recognition Mode
with the 7-bit I
to recognize the incoming slave address.
Configuring the SBI as a Master or a Slave
slave. This bit is cleared by hardware when a STOP condition has been detected and when arbitration
for the I
Internal SCL Level (Master B)
SCL Bus Line
When the SBI is configured to operate as a slave, the SA[6:0] field in the I2C0AR must be loaded
Setting the SBI0CR2.MST bit configures the SBI as a master, and clearing it configures the SBI as a
Internal SCL Level (Master A)
to the bus. If two or more masters try to transfer messages on the I
line low wins the arbitration, overriding other masters producing a high on their clock lines.
transfers. Figure 14.8 shows a depiction of the clock synchronization mechanism for the I
with two masters.
to-low transition on the SCL bus line causes Master B to reset its high-level counter and pulls its
internal SCL level low.
SCL level does not change the state of the SCL bus line if Master B’s internal SCL level is still
within its low period. Therefore, Master A enters a high wait state, where it does not start counting
off its high period.
releasing the SCL bus line (high). There will then be no difference between the internal SCL levels
and the state of the SCL bus line, and both Master A and Master B start counting off their high
periods.
with the shortest clock high period and its low period determined by the one with the longest clock
low period.
Clock synchronization is performed using the wired-AND connection of all I
Clock signals of two or more devices on the I
At point a, Master A pulls its internal SCL level low, bringing the SCL bus line low. The high-
Master A completes its low period at point b. However, the low-to-high transition on its internal
When Master B has counted off its low period at point c, its internal SCL level goes high,
This way, a synchronized SCL clock is generated with its high period determined by the master
2
C bus has been lost.
2
C-bus address to which the SBI is to respond. The ALS bit must be cleared for the SBI
Figure 14.8 Clock Synchronization Example
TMP1940CYAF-206
a
Counter reset
b
Wait State
2
C-bus are synchronized to ensure correct data
c
Start counting HIGH period
2
C bus, the first to pull its clock
TMP1940CYAF
2
C-bus components
2
C bus