EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 1019
EP4SE530H35C2N
Manufacturer Part Number
EP4SE530H35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4SE530H35C2N
Manufacturer:
ALTERA
Quantity:
147
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and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but
reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any
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SIV53002-4.1
Stratix IV Device Handbook Volume 3
February 2011
February 2011
SIV53002-4.1
This chapter describes the Altera-recommended basic design flow that simplifies
Stratix
Use the following design flow techniques to simplify transceiver implementation. The
“Guidelines to Debug Transceiver-Based Designs” on page 2–14
to trouble-shoot transceiver-based designs. An example of a fibre channel protocol
application is also described in this chapter.
The transceiver-based design is divided into phases and are detailed in the following
sections:
■
■
■
■
■
■
Figure 2–1
design flow stages include architecture, functional simulation, compilation, and
verification. Each stage of the design flow is explained in the sections that follow.
“Architecture” on page 2–3
“Implementation and Integration” on page 2–6
“Compilation” on page 2–10
“Verification” on page 2–12
“Functional Simulation” on page 2–12
“Example 1: Fibre Channel Protocol Application” on page 2–17
®
IV GX transceiver-based designs.
shows the design flow chart of the different stages of the design flow. The
2. Transceiver Design Flow Guide for
Stratix IV Devices
provides guidelines
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