EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 690
EP4SE530H35C2N
Manufacturer Part Number
EP4SE530H35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
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Part Number:
EP4SE530H35C2N
Manufacturer:
ALTERA
Quantity:
147
- EP4SGX110DF29C3N PDF datasheet
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- EP4SE230F29C3N PDF datasheet #6
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2–18
Stratix IV Device Handbook Volume 2: Transceivers
Figure 2–12
configured in Basic (PMA Direct) ×N mode running at 6.5 Gbps with a 20-bit FPGA
fabric-PMA interface width. Because all 24 channels on the right side of the device are
configured in Basic (PMA Direct) ×N mode, use the right PLL_R1 configured in VCO
bypass mode to provide the input reference clock to the 6G ATX PLL.
Because the data rate of 6.5 Gbps requires a left and right, left, or right PLL to meet
FPGA fabric-Transmitter PMA interface timing, the tx_clkout from one of the 24
channels is phase shifted using PLL_R2. Use the phase-shifted output clock from
PLL_R2 to clock the FPGA fabric logic that generates the transmitter parallel data and
control signals.
shows 24 channels on the right side of the EP4SGX530NF45 device
Chapter 2: Transceiver Clocking in Stratix IV Devices
FPGA Fabric PLLs-Transceiver PLLs Cascading
February 2011 Altera Corporation
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