EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 657

• Manufacturer Part Number: EP4SE530H35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Port Lists
Table 1–74. Stratix IV GX and GT ALTGX Megafunction Ports: Receiver Ports (Part 2 of 7)
February 2011 Altera Corporation
rx_invpolarity
rx_revbitorderwa
rx_revbyteorderwa
Port Name
Output
Input/
Input
Input
Input
pulse width is two
pulse width is two
pulse width is two
Signal. Minimum
Signal. Minimum
Signal. Minimum
Asynchronous
Asynchronous
Asynchronous
Clock Domain
parallel clock
parallel clock
parallel clock
cycles.
cycles.
cycles.
Generic receiver polarity inversion control.
Useful feature for correcting situations where
the positive and negative signals of the
differential serial link are accidentally swapped
during board layout.
■
■
Receiver bit reversal control. This is a useful
feature where the link transmission order is
MSB to LSB.
■
■
■
Receiver byte reversal control. This is a useful
feature in situations where the MSByte and
LSByte of the transmitted data are erroneously
swapped.
■
■
When asserted high in single-width
modes—the polarity of every bit of the 8-bit
or 10-bit input data word to the word aligner
gets inverted.
When asserted high in double-width
modes—the polarity of every bit of the
16-bit or 20-bit input data to the word
aligner gets inverted.
Available only in Basic single-width and
double-width modes with the word aligner
configured in bit-slip mode.
When asserted high in Basic single-width
modes—the 8-bit or 10-bit data D[7:0] or
D[9:0] at the output of the word aligner
gets rewired to D[0:7] or D[0:9],
respectively.
When asserted high in Basic double-width
modes—the 16-bit or 20-bit data D[15:0]
or D[19:0] at the output of the word aligner
gets rewired to D[0:15] or D[0:19],
respectively.
Available only in Basic double-width mode.
When asserted high, the MSByte and LSByte
of the 16- and 20-bit data at the output of the
word aligner get swapped.
Stratix IV Device Handbook Volume 2: Transceivers
Description
Channel
Channel
Channel
Scope
1–213