EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 370
EP4SE530H35C2N
Manufacturer Part Number
EP4SE530H35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
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Company:
Part Number:
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Manufacturer:
ALTERA
Quantity:
147
- EP4SGX110DF29C3N PDF datasheet
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- EP4SE230F29C3N PDF datasheet #6
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10–36
Figure 10–16. JTAG Configuration of a Single Device Using a Download Cable
Notes to
(1) Connect the pull-up resistor to the same supply voltage as the USB Blaster, MasterBlaster (VIO pin), ByteBlaster II, ByteBlasterMV, or
(2) Connect the nCONFIG and MSEL[2..0] pins to support a non-JTAG configuration scheme. If you only use the JTAG configuration, connect
(3) Pin 6 of the header is a V
(4) You must connect nCE to GND or driven low for successful JTAG configuration.
(5) The pull-up resistor value can vary from 1 k to 10 kΩ.
Stratix IV Device Handbook Volume 1
EthernetBlaster cable. The voltage supply can be connected to the V
nCONFIG to V
this value, refer to the
this pin is a no connect.
Figure
10–16:
CCPGM
and MSEL[2..0] to GND. Pull DCLK either high or low, whichever is convenient on your board.
MasterBlaster Serial/USB Communications Cable User
V
During JTAG configuration, you can download data to the device on the PCB through
the USB Blaster, MasterBlaster, ByteBlaster II, EthernetBlaster, or ByteBlasterMV
download cable. Configuring devices through a cable is similar to programming
devices in-system, except you must connect the TRST pin to V
the TAP controller is not reset.
Figure 10–16
download cable.
CCPGM
IO
reference voltage for the MasterBlaster output driver. V
10
kΩ
V
CCPGM
GND
10
(2)
(2)
(2)
kΩ
N.C.
shows JTAG configuration of a single Stratix IV device when using a
Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
nCE
nCE0
CONF_DONE
nCONFIG
MSEL[2..0]
DCLK
nSTATUS
Stratix IV Device
(4)
TRST
TDO
TMS
TCK
TDI
CCPD
V
CCPD
V
(5)
of the device.
CCPD
(1)
V
Guide. In the USB-Blaster, ByteBlaster II, and ByteBlasterMV cable,
CCPD
(1)
(5)
IO
(1)
1
must match the device’s V
kΩ
GND
Pin 1
10-Pin Male Header
Download Cable
(JTAG Mode)
(Top View)
GND
V
CCPD
V
IO
CCPD
(1)
(3)
CCPD
GND
April 2011 Altera Corporation
. For more information about
. This ensures that
JTAG Configuration
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