EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 654
![no-image](/images/manufacturer_photos/0/0/40/altera_sml.jpg)
EP4SE530H35C2N
Manufacturer Part Number
EP4SE530H35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4SE530H35C2N
Manufacturer:
ALTERA
Quantity:
147
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
- Current page: 654 of 1154
- Download datasheet (32Mb)
1–210
Table 1–73. Stratix IV GX and GT ALTGX Megafunction Ports: Transmitter Ports (Part 2 of 3)
Stratix IV Device Handbook Volume 2: Transceivers
8B/10B Encoder
tx_ctrlenable
tx_forcedisp
tx_dispval
Port Name
Output
Input/
Input
Input
Input
pulse width is two
pulse width is two
signal. Minimum
signal. Minimum
Synchronous to
Asynchronous
Asynchronous
Clock Domain
parallel clock
parallel clock
tx_clkout/
coreclkout
clock signal.
cycles.
cycles.
8B/10B encoder /Kx.y/ or /Dx.y/ control.
■
■
■
8B/10B encoder force disparity control.
■
■
■
8B/10B encoder force disparity value.
■
■
■
When asserted high—the 8B/10B encoder
encodes the data on the tx_datain port as
a /Kx.y/ control code group.
When de-asserted low—it encodes the data
on the tx_datain port as a /Dx.y/ data code
group.
Channel Width:
8—tx_ctrlenable = 1
16—tx_ctrlenable = 2
32—tx_ctrlenable = 4
When asserted high—forces the 8B/10B
encoder to encode the data on the
tx_datain port with a positive or negative
disparity depending on the tx_dispval
signal level.
When de-asserted low—the 8B/10B encoder
encodes the data on the tx_datain port
according to the 8B/10B running disparity
rules.
Channel Width:
8—tx_forcedisp = 1
16—tx_forcedisp = 2
32—tx_forcedisp = 4
A high level—when the tx_forcedisp
signal is asserted high, it forces the 8B/10B
encoder to encode the data on the
tx_datain port with a negative starting
running disparity.
A low level—when the tx_forcedisp
signal is asserted high, it forces the 8B/10B
encoder to encode the data on the
tx_datain port with a positive starting
running disparity.
Channel Width:
8—tx_dispval = 1
16—tx_dispval = 2
32—tx_dispval = 4
Chapter 1: Transceiver Architecture in Stratix IV Devices
Description
February 2011 Altera Corporation
Transceiver Port Lists
Channel
Channel
Channel
Scope
Related parts for EP4SE530H35C2N
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![DK-CYCII-2C20N](/photos/9/20/92074/mfgdk-cycii-2c20nboard_tmb.jpg)
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
![EP610PC-35](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-15](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP610IPC-25](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-30](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-10](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-7](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-12](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-10A](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
![P85C224-66](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP320PC](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP2A15B724C7](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-25T](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: