EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 900
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EP4SE530H35C2N
Manufacturer Part Number
EP4SE530H35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4SE530H35C2N
Manufacturer:
ALTERA
Quantity:
147
- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
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5–54
Figure 5–26. CMU PLLs in a Transceiver Block in CMU PLL Reconfiguration Mode
Note to
(1) Depending on the mode you select, PCS may or may not be present.
Stratix IV Device Handbook Volume 2: Transceivers
Figure
refclk0
refclk1
5–26:
1
The dynamic reconfiguration controller powers down only the selected CMU PLL.
The other CMU PLL is not affected.
Blocks Reconfigured in CMU PLL Reconfiguration Mode
Each transceiver block has two CMU PLLs—CMU0 PLL and CMU1 PLL.You can
reconfigure each of these CMU PLLs to a different data rate in this mode.
shows a view of the reconfigurable blocks using CMU PLL reconfiguration mode.
ALTGX MegaWizard Plug-In Manager Setup for CMU PLL Reconfiguration Mode
If you want to reconfigure the CMU PLL to another data rate, enable .mif generation
and set up the ALTGX MegaWizard Plug-In Manager, as described in the following
steps. The dynamic reconfiguration controller reconfigures the CMU PLL with the
new information stored in the .mif.
1. Select the Channel and Transmitter PLL reconfiguration option in the Modes
2. Provide the new data rate you want the CMU PLL to run at in the General screen.
The logical reference index of CMU0 PLL within a transceiver block is always the
complement of the logical reference index of CMU1 PLL.
screen.
clock
mux
clock
mux
CMU Channels
CMU0 PLL
CMU1 PLL
Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Logical
TX PLL
select
clock
mux
Full Duplex Transceiver Channel
Dynamic Reconfiguration Modes Implementation
LOCAL
DIVIDER
TX CHANNEL
RX CHANNEL
RX CDR
February 2011 Altera Corporation
TX PMA + TX PCS
RX PMA + RX PCS
(1)
Figure 5–26
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