EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 692
EP4SE530H35C2N
Manufacturer Part Number
EP4SE530H35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4SE530H35C2N
Manufacturer:
ALTERA
Quantity:
147
- EP4SGX110DF29C3N PDF datasheet
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- EP4SE230F29C3N PDF datasheet #6
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2–20
Transceiver Channel Datapath Clocking
Stratix IV Device Handbook Volume 2: Transceivers
Transmitter Channel Datapath Clocking
f
1
This section describes the transmitter channel and receiver channel datapath clocking
in various configurations. Datapath clocking varies with physical coding sublayer
(PCS) configurations in different functional modes as well as channel bonding
options. This section contains:
■
■
Clocking described in this section is internal to the transceiver and clock routing is
primarily performed by the Quartus II software.
For more information about manually picking and placing CMU and ATX PLLs, refer
to
Devices.
This section describes the transmitter channel PMA and PCS datapath clocking in
non-bonded and bonded channel configurations:
■
■
■
■
AN 578: Manual Placement of CMU PLLs and ATX PLLs in Stratix IV GX and GT
“Transmitter Channel Datapath Clocking” on page 2–20
“Receiver Channel Datapath Clocking” on page 2–39
“Non-Bonded Channel Configurations” on page 2–24
“Bonded Channel Configurations” on page 2–27
“Non-Bonded Basic (PMA Direct) Mode Channel Configurations” on page 2–34
“Bonded Basic (PMA Direct) ×N Mode Channel Configurations” on page 2–36
Chapter 2: Transceiver Clocking in Stratix IV Devices
Transceiver Channel Datapath Clocking
February 2011 Altera Corporation
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