EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 801
EP4SE530H35C2N
Manufacturer Part Number
EP4SE530H35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4SE530H35C2N
Manufacturer:
ALTERA
Quantity:
147
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- EP4SE230F29C3N PDF datasheet #6
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Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices
Combining Transceiver Channels When You Enable the Adaptive Equalization (AEQ) Feature
Combining Transceiver Channels When You Enable the Adaptive
Equalization (AEQ) Feature
February 2011 Altera Corporation
f
Create three Instances for steps 1, 2, and 3 with the following parameters:
Instance 1
■
■
Table 3–20. Instance 1 for Example 13
Instance 2
■
■
Table 3–21. Instance 2 for Example 13
Instance 3
■
■
Table 3–22. Instance 3 for Example 13
For more information, refer to
Alternate CMU PLL Option” on page
To enable the AEQ feature in a transceiver channel, select the Enable Adaptive
Equalization option in the Reconfig screen of the ALTGX MegaWizard Plug-In
Manager. When you select this option, the aeq_fromgxb and aeq_togxb ports are
enabled.
For more information about initiating the AEQ feature, refer to the “Adaptive
Equalization (AEQ)” section in the
chapter.
Select the use additional CMU/ATX Transmitter PLLs from outside the
transceiver block option.
Number of additional PLLs: 3
Select the use additional CMU/ATX Transmitter PLLs from outside the
transceiver block option.
Number of additional PLLs: 0
Select the use additional CMU/ATX Transmitter PLLs from outside the
transceiver block option.
Number of additional PLLs: 0
Main PLL
Main PLL
Main PLL
PLL1
PLL2
PLL3
PLL
PLL
PLL
“Combination Requirements When You Enable the Use
(Table
(Table
(Table
Dynamic Reconfiguration in Stratix IV Devices
SONET OC48
SONET OC48
3–42.
Data Rate
Data Rate
Data Rate
FC 2G
3–20)
OTU1
3–21)
3–22)
GIGE
GIGE
Stratix IV Device Handbook Volume 2: Transceivers
PLL Logical Reference Index
PLL Logical Reference Index
PLL Logical Reference Index
0
1
2
3
3
2
3–47
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