EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 875
EP4SE530H35C2N
Manufacturer Part Number
EP4SE530H35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Manufacturer
Quantity
Price
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Part Number:
EP4SE530H35C2N
Manufacturer:
ALTERA
Quantity:
147
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Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Modes Implementation
Figure 5–16. Logical Reference Index of CMU PLLs in a Transceiver Block
Note to
(1) After the device powers up, the busy signal remains low for the first reconfig_clk cycle.
February 2011 Altera Corporation
Figure
refclk0
refclk1
5–16:
156.25 MHz
125 MHz
In
Similarly, transceiver channel 2 listens to CMU1 PLL of the transceiver block.
To direct the ALTGX_RECONFIG instance to dynamically reconfigure CMU0 PLL,
specify its logical reference index (the identity of a transmitter PLL). Similarly, to
direct the ALTGX_RECONFIG instance to dynamically reconfigure CMU1 PLL instead,
provide the logical reference index of CMU1 PLL. The allowed values for the logical
reference index of the CMU PLLs within a transceiver block are 0 or 1. Similarly, the
transmitter PLLs outside the transceiver block can also be assigned a logical reference
index value. For more information, refer to
Index for Additional PLLs” on page
Figure
Selecting the Logical Reference Index of the CMU PLL
5–16, transceiver channel 1 listens to CMU0 PLL of the transceiver block.
clock
mux
clock
mux
CMU Channels
6.25 Gbps
CMU0 PLL
2.5 Gbps
CMU1 PLL
5–52.
“Selecting the PLL Logical Reference
Logical
TX PLL
select
TX PLL
Logical
clock
mux
select
(Note 1)
clock
mux
Stratix IV Device Handbook Volume 2: Transceivers
Full Duplex Transceiver Channel 1
Full Duplex Transceiver Channel 2
DIVIDER
LOCAL
6.25 Gbps
TX CHANNEL 1
RX CHANNEL 1
DIVIDER
RX CDR
RX CHANNEL 2
TX CHANNEL 2
LOCAL
RX CDR
2.5 Gbps
TX PMA + TX PCS
RX PMA + RX PCS
TX PMA + TX PCS
RX PMA + RX PCS
6.25 Gbps
6.25 Gbps
2.5 Gbps
2.5 Gbps
5–29
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