EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 477

• Manufacturer Part Number: EP4SE530H35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–29. Serializer Block in 8-Bit PCS-PMA Interface
Note to
(1) The CMU0 clock divider of the master transceiver block provides the clocks. It is used only in bonded modes (for example, Basic ×8, PCIe ×8 mode).
Figure 1–30. Serializer Bit Order
Note to
(1) It is assumed that the input data to the serializer is 8 bits (channel width = 8 bits or 16 bits with the 8B/10B encoder disabled).
February 2011 Altera Corporation
parallel clock from master transceiver block (1)
serial clock from master transceiver block (1)
Figure
Figure
parallel clock from CMU0 clock divider
1–29:
1–30:
parallel clock from local divider block
serial clock from CMU0 clock divider
serial clock from local divider block
Figure 1–30
constant 8'h6A (01101010) value is serialized and the serial data is transmitted from
LSB to MSB.
Low-speed parallel clock
High-speed serial clock
tx_datain[7..0]
tx_dataout[0]
(Note 1)
shows the serial bit order of the serializer block output. In this example, a
01101010
0 1 0
8
Parallel Clock
Low-Speed
1
High-Speed Serial Clock
0
1 1
0
D7
D6
D5
D4
D3
D2
D1
D0
00000000
Stratix IV Device Handbook Volume 2: Transceivers
D7
D6
D5
D4
D3
D2
D1
D0
To Output Buffer
1–33