EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 192
EP4SE530H35C2N
Manufacturer Part Number
EP4SE530H35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4SE530H35C2N
Manufacturer:
ALTERA
Quantity:
147
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6–20
Stratix IV Device Handbook Volume 1
High-Speed Differential I/O with DPA Support
Programmable Current Strength
f
Stratix IV devices have the following dedicated circuitry for high-speed differential
I/O support:
■
■
■
■
■
■
■
For more information about DPA support, refer to the
Interfaces and DPA in Stratix IV Devices
The output buffer for each Stratix IV device I/O pin has a programmable current
strength control for certain I/O standards. Use programmable current strength to
mitigate the effects of high signal attenuation due to a long transmission line or a
legacy backplane. The LVTTL, LVCMOS, SSTL, and HSTL standards have several
levels of current strength that you can control.
current strength for Stratix IV devices.
Table 6–3. Programmable Current Strength (Part 1 of 2)
3.3-V LVTTL
3.3-V LVCMOS
2.5-V LVCMOS
1.8-V LVCMOS
1.5-V LVCMOS
1.2-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
SSTL-15 Class I
SSTL-15 Class II
HSTL-18 Class I
HSTL-18 Class II
HSTL-15 Class I
HSTL-15 Class II
Differential I/O buffer
Transmitter serializer
Receiver deserializer
Data realignment
Dynamic phase aligner (DPA)
Synchronizer (FIFO buffer)
Phase-locked loops (PLLs)
I/O Standard
I
OH
chapter.
/ I
Setting (mA) for
Column I/O Pins
12, 10, 8, 6, 4, 2
12, 10, 8, 6, 4, 2
OL
12, 10, 8, 6, 4
12, 10, 8, 6, 4
12, 10, 8, 6, 4
12, 10, 8, 6, 4
16, 12, 8, 4
16, 12, 8, 4
16, 12, 8, 4
Current Strength
8, 6, 4, 2
12, 10, 8
16, 8
16, 8
16
16
16
Table 6–3
(Note
Chapter 6: I/O Features in Stratix IV Devices
High-Speed Differential I/O
1),
lists the programmable
(2)
February 2011 Altera Corporation
I
OH
/ I
Setting (mA) for
OL
12, 10, 8, 6, 4
12, 10, 8, 6, 4
Row I/O Pins
Current Strength
8, 6, 4, 2
8, 6, 4, 2
12, 8, 4
12, 8, 4
8, 6, 4
8, 6, 4
12, 8
16, 8
8, 4
4, 2
16
—
16
—
I/O Structure
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