EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 689
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EP4SE530H35C2N
Manufacturer Part Number
EP4SE530H35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4SE530H35C2N
Manufacturer:
ALTERA
Quantity:
147
- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
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Chapter 2: Transceiver Clocking in Stratix IV Devices
FPGA Fabric PLLs-Transceiver PLLs Cascading
Figure 2–11. Left and Right, Left, or Right PLL in VCO Bypass Mode
February 2011 Altera Corporation
from the dedicated
Reference clock
CLK pin
Left and Right, Left, or Right PLL in VCO Bypass Mode
f
If all CMU channels on the same side of the device are configured as channels, all
refclk pins are used as receiver serial input data pins. All CMU PLLs are also used as
receiver CDRs. In such designs, you must use the 6G ATX PLLs to generate the
high-speed serial and low-speed parallel transceiver clocks provided that the
configured data rate is supported by the 6G ATX PLLs. Additionally, Altera
recommends providing the input reference clock to the 6G ATX PLL using the left or
right PLL cascade clock line because none of the refclk pins are available. To avoid
jitter amplification because of cascading of the left or right PLL to the 6G ATX PLL,
you must place the left or right PLL in VCO bypass mode.
For more information about CMU PLLs, refer to “Configuring CMU Channels as
Transceiver Channels” in the
Figure 2–11
dedicated FPGA CLK pins to the inclk port of the left and right, left, or right PLL
bypasses the PLL loop and is driven directly on the PLL output clock port.
/N
shows that in VCO bypass mode, the input reference clock from the
Frequency
Detector
Phase
Transceiver Architecture in Stratix IV Devices
Charge Pump
Left and Right PLL
Loop Filter
+
/M
Controlled
Oscillator
Voltage
Stratix IV Device Handbook Volume 2: Transceivers
C1
chapter.
Input reference
6G ATX PLL
clock to the
2–17
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