EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 967
EP4SE530H35C2N
Manufacturer Part Number
EP4SE530H35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4SE530H35C2N
Manufacturer:
ALTERA
Quantity:
147
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Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Parameter Settings
Table 1–1. MegaWizard Plug-In Manager Options (General Screen for Basic Mode) (Part 6 of 10)
February 2011 Altera Corporation
What is the channel width?
ALTGX Setting
Basic
Deterministic Latency
This option determines the FPGA fabric-Transceiver
interface width.
■
■
Basic (PMA Direct)
This option determines the FPGA fabric-Transceiver
interface width.
■
■
GIGE
This option determines the FPGA fabric-Transceiver
interface width. In GIGE mode, only 8 bits are allowed.
(OIF) CEI PHY Interface
This option selects the FPGA fabric-Transceiver width. In
(OIF) CEI PHY Interface mode, only 32 bits are allowed.
PCIe
This option determines the FPGA fabric-Transceiver
interface width.
■
■
SDI
This option determines the FPGA fabric-Transceiver
interface width:
■
■
■
■
Serial RapidIO
The channel width is fixed to 16 in Serial RapidIO mode.
Single-width mode—Selecting 8 or 10 bits bypasses
the byte serializer/deserializer. Selecting 16 or 20 bits
uses the byte serializer/deserializer.
Double-width mode—Selecting 16 or 20 bits
bypasses the byte serializer/deserializer. Selecting 32
or 40 bits uses the byte serializer/deserializer.
Single-width mode—You can select 8 or 10 bits.
Double-width mode— You can select 16 or 20 bits.
In PCIe Gen1 (2.5 Gbps) mode, 8 and 16 bits are
allowed.
In PCIe Gen2 (5 Gbps) mode, only 16 bits are allowed.
HD mode—10-bit and 20-bit channel widths are
allowed.
3G mode—only 20-bit channel width is allowed.
10-bit configuration—the byte serializer is not used.
20-bit configuration—the byte serializer is used.
Description
“Byte Serializer” and “Byte
Deserializer” sections in the
Transceiver Architecture in
Stratix IV Devices
Stratix IV Device Handbook Volume 3
Reference
chapter.
1–9
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