EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 275
EP4SE530H35C2N
Manufacturer Part Number
EP4SE530H35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
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Part Number:
EP4SE530H35C2N
Manufacturer:
ALTERA
Quantity:
147
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Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
February 2011 Altera Corporation
I/O Configuration Block and DQS Configuration Block
The I/O configuration block and the DQS configuration block are shift registers that
you can use to dynamically change the settings of various device configuration bits.
The shift registers power-up low. Every I/O pin contains one I/O configuration
register, while every DQS pin contains one DQS configuration block in addition to the
I/O configuration register.
DQS configuration block circuitry.
Figure 7–36. I/O Configuration Block and DQS Configuration Block
Table 7–19
Table 7–19. I/O Configuration Block Bit Sequence
Table 7–20
Table 7–20. DQS Configuration Block Bit Sequence (Part 1 of 2)
11..14
15..18
19..22
27..29
30..33
7..10
7..10
0..3
4..6
0..3
4..6
Bit
Bit
23
24
25
26
lists the I/O configuration block bit sequence.
lists the DQS configuration block bit sequence.
update
datain
ena
clk
Figure 7–36
bit 0
bit 1
shows the I/O configuration block and the
padtoinputregisterdelaysetting[0..3]
dqsenablectrlphasesetting[0..3]
resyncinputphasesetting[0..3]
dqsoutputphasesetting[0..3]
dqsbusoutdelaysetting[0..3]
dqsenabledelaysetting[0..2]
dqsinputphasesetting[0..2]
dqoutputphasesetting[0..3]
enaoutputcycledelaysetting
bit 2
enainputcycledelaysetting
outputdelaysetting1[0..3]
outputdelaysetting2[0..2]
enaoctcycledelaysetting
octdelaysetting1[0..3]
dividerphasesetting
Bit Name
Bit Name
Stratix IV Device Handbook Volume 1
MSB
7–55
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