EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 227
EP4SE530H35C2N
Manufacturer Part Number
EP4SE530H35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
EP4SE530H35C2N
Manufacturer:
ALTERA
Quantity:
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Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
Table 7–2. Number of DQS/DQ Groups in Stratix IV Devices per Side (Part 3 of 3)
February 2011 Altera Corporation
EP4S100G3
EP4S100G4
EP4S100G5
Notes to
(1) These numbers are preliminary until the devices are available.
(2) Some of the ×4 groups may use R
(3) To interface with a ×36 QDR II+/QDR II SRAM device in a Stratix IV FPGA that does not support the ×32/×36 DQS/DQ group, refer to
(4) These ×32/×36 DQS/DQ groups have 40 pins instead of 48 pins per group. BWSn pins cannot be placed within the same DQS/DQ group as the
×16/×18 DQS/DQ Groups for a ×36 QDR II+/QDR II SRAM Interface” on page
write data pins because of insufficient pins available.
Device
Table
7–2:
1932-pin
FineLine BGA
Package
UP
and R
Top/Bottom
DN
pins. You cannot use these groups if you use the Stratix IV calibrated OCT feature.
Right
Side
Left
×4
38
8
7
(2)
×8/×9
7–26.
18
2
1
×16/×18
(Note 1)
0
8
0
Stratix IV Device Handbook Volume 1
×32/×36
0
4
0
(3)
Figure 7–19
Refer to:
“Combining
7–7
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