EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 85
EP4SE530H35C2N
Manufacturer Part Number
EP4SE530H35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Manufacturer
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Part Number:
EP4SE530H35C2N
Manufacturer:
ALTERA
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Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV Simplified DSP Operation
Figure 4–3. Four-Multiplier Adder and Accumulation Capability
February 2011 Altera Corporation
Input
Data
144
Following the two-multiplier adder units are the pipeline registers, the second-stage
adders, and an output register stage. You can configure the second-stage adders to
provide the alternative functions per half block, as shown in
Equation
Equation 4–2. Four-Multiplier Adder Equation
Equation 4–3. Four-Multiplier Adder Equation (44-Bit Accumulation)
In these equations, n denotes sample time and P[36..0] denotes the result from the
two-multiplier adder units.
Equation 4–2
(four-multiplier adder).
operation but with a maximum 44-bit accumulation capability by feeding the output
of the unit back to itself, as shown in
Depending on the mode you select, you can bypass all register stages except
accumulation and loopback mode. In these two modes, one set of registers must be
enabled. If the register set is not enabled, an infinite loop occurs.
Half-DSP Block
4–3.
provides a sum of four 18 × 18-bit multiplication operations
Equation 4–3
W
Z[37..0] = P
n
[43..0] = W
Figure
provides a four 18 × 18-bit multiplication
0
n-1
[36..0] + P
[43..0] ± Z
4–3.
1
[36..0]
n
[37..0]
Stratix IV Device Handbook Volume 1
Equation 4–2
44
Result[]
and
4–5
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