EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 401
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EP4SE530H35C2N
Manufacturer Part Number
EP4SE530H35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4SE530H35C2N
Manufacturer:
ALTERA
Quantity:
147
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Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
Design Security
April 2011 Altera Corporation
Security Modes Available
At system power-up, the external memory device sends the encrypted configuration
file to the Stratix IV device.
Figure 10–29. Design Security
Note to
(1) Step 1, Step 2, and Step 3 correspond to the procedure described in
The following security modes are available on the Stratix IV device.
Volatile Key
Secure operation with volatile key programmed and required external battery: this
mode accepts both encrypted and unencrypted configuration bitstreams. Use the
unencrypted configuration bitstream support for board-level testing only.
Non-Volatile Key
Secure operation with one time programmable (OTP) security key programmed: this
mode accepts both encrypted and unencrypted configuration bitstreams. Use the
unencrypted configuration bitstream support for board level testing only.
Non-Volatile Key with Tamper Protection Bit Set
Secure operation in tamper resistant mode with OTP security key programmed: only
encrypted configuration bitstreams are allowed to configure the device. Tamper
protection disables JTAG configuration with unencrypted configuration bitstream.
Figure
10–29:
User-Defined
Configuration
Encrypted
AES Key
File
(Note 1)
Step 2
Step 1
“Design Security” on page
Configuration
Stratix IV Device
Memory or
Key Storage
Decryption
Stratix IV Device Handbook Volume 1
Device
AES
Step 3
10–63.
10–67
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