EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 504
EP4SE530H35C2N
Manufacturer Part Number
EP4SE530H35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4SE530H35C2N
Manufacturer:
ALTERA
Quantity:
147
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1–60
Figure 1–49. Word Aligner in All Supported Configurations
Stratix IV Device Handbook Volume 2: Transceivers
Basic Single-Width)
(OC-12, OC-48,
Alignment
Manual
8-Bit Wide
Single-Width)
Bit-Slip
(Basic
Figure 1–49
In single-width mode, the PMA-PCS interface is either 8 or 10 bits wide. In 8-bit wide
PMA-PCS interface modes, the word aligner receives 8-bit wide data from the
deserializer. In 10-bit wide PMA-PCS interface modes, the word aligner receives
10-bit wide data from the deserializer. Depending on the configured functional mode,
you can configure the word aligner in manual alignment mode, automatic
synchronization state machine mode, or bit-slip mode.
The following functional modes support the 8-bit PMA-PCS interface:
■
■
■
Table 1–26
8-bit PMA-PCS interface.
Table 1–26. Word Aligner Configurations with an 8-Bit PMA-PCS Interface
In manual alignment mode, the word aligner operation is controlled by the input
signal rx_enapatternalign. The word aligner operation is edge-sensitive to the
rx_enapatternalign signal. After de-assertion of rx_digitalreset, a rising edge on
the rx_enapatternalign signal triggers the word aligner to look for the word
alignment pattern in the received data stream. In SONET/SDH OC-12 and OC-48
modes, the word aligner looks for 16'hF628 (A1A2) or 32'hF6F62828 (A1A1A2A2),
SONET/SDH OC-12
SONET/SDH OC-48
Basic single-width
SONET/SDH OC-12
SONET/SDH OC-48
Basic single-width
Word Aligner in Single-Width Mode
Functional Mode
Single-Width)
Alignment
Single-Width
Word Aligner in Single-Width Mode with 8-Bit PMA-PCS Interface Modes
Manual Alignment Mode Word Aligner with 8-Bit PMA-PCS Interface Modes
Manual
(Basic
lists the word aligner configurations allowed in functional modes with an
shows the word aligner operation in all supported configurations.
Basic Single-Width,
Synchronization
Serial RapidIO)
State Machine
XAUI, GIGE,
Automatic
(PCIe
10-Bit Wide
(Basic Single-Width,
Bit-Slip
Allowed Word Configurations
SDI)
PMA-PCS Interface Width
Manual Alignment, Bit-Slip
Manual Alignment
Manual Alignment
Double-Width,
Alignment
Manual
OC-96)
(Basic
Chapter 1: Transceiver Architecture in Stratix IV Devices
16-Bit Wide
Double-Width)
Bit-Slip
(Basic
Double-Width
February 2011 Altera Corporation
Allowed Word Alignment
Double-Width)
Alignment
Transceiver Block Architecture
Manual
(Basic
Pattern Length
16 bits
16 bits
16 bits
20-Bit Wide
Double-Width)
Bit-Slip
(Basic
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