EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 728
EP4SE530H35C2N
Manufacturer Part Number
EP4SE530H35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4SE530H35C2N
Manufacturer:
ALTERA
Quantity:
147
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2–56
Stratix IV Device Handbook Volume 2: Transceivers
Limitations of the Quartus II Software-Selected Transmitter Phase Compensation FIFO Write
Clock
The Quartus II software uses a single tx_clkout signal to clock the transmitter phase
compensation FIFO write port of all identical channels within a transceiver block.
This results in one global and/or regional clock resource being used for each group of
identical channels within a transceiver block.
For identical channels located across the transceiver blocks, the Quartus II software
does not use a single tx_clkout signal to clock the write port of the transmitter phase
compensation FIFOs for all channels. It uses one tx_clkout signal for each group of
identical channels per transceiver block. This results in higher global and regional
clock resource usage.
Example 4: Sixteen Identical Channels Across Four Transceiver Blocks
Figure 2–31
blocks. The Quartus II software uses tx_clkout from Channel 0 in each transceiver
block to clock the write port of the transmitter phase compensation FIFO in all four
channels in that transceiver block. This results in four global and/or regional clock
resources being used, one for each transceiver block.
shows 16 identical transmitter channels located across four transceiver
Chapter 2: Transceiver Clocking in Stratix IV Devices
FPGA Fabric-Transceiver Interface Clocking
February 2011 Altera Corporation
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