EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 280
EP4SE530H35C2N
Manufacturer Part Number
EP4SE530H35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
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Company:
Part Number:
EP4SE530H35C2N
Manufacturer:
ALTERA
Quantity:
147
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8–2
Figure 8–1. I/O Bank Support in the Stratix IV Device Family
Notes to
(1) Column input buffers are true LVDS buffers, but do not support 100-Ω differential on-chip termination.
(2) Column output buffers are single ended and need external termination schemes to support LVDS, mini-LVDS, and RSDS standards. For more
(3) Row input buffers are true LVDS buffers and support 100-Ω differential on-chip termination.
(4) Row output buffers are true LVDS buffers.
Stratix IV Device Handbook Volume 1
information, refer to the
Figure
with 'Use External PLL'
Option Enabled
LVDS Interface
8–1:
■
■
■
■
For high-speed differential interfaces, the Stratix IV device family supports the
following differential I/O standards:
■
■
■
In the Stratix IV device family, I/Os are divided into row and column I/Os.
shows I/O bank support for the Stratix IV device family. The row I/Os provide
dedicated SERDES circuitry.
I/O Features in Stratix IV Devices
Data realignment
DPA
Synchronizer (FIFO buffer)
Phase-locked loops (PLLs) (located on left and right sides of the device)
LVDS
Mini-LVDS
Reduced swing differential signaling (RSDS)
SERDES Circuitry (3), (4)
Row I/Os with
Dedicated
chapter.
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
with 'Use External PLL'
Option Disabled
LVDS Interface
(Note
LVDS I/Os
1), (2), (3),
(4)
February 2011 Altera Corporation
Column I/Os (1), (2)
Figure 8–1
Overview
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