EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 768
EP4SE530H35C2N
Manufacturer Part Number
EP4SE530H35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Price
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Part Number:
EP4SE530H35C2N
Manufacturer:
ALTERA
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147
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3–14
Table 3–7. Two ALTGX Instances for Example 4
Stratix IV Device Handbook Volume 2: Transceivers
Instance Name
inst0
inst1
Example 4
Consider the design example configuration listed in
instances.
In this case, assuming that all the required parameters specified in
Channels Sharing a CMU PLL” on page 3–5
Quartus II software fits inst0 and inst1 in two transceiver blocks.
Figure 3–5
compilation.
Figure 3–5. Transceiver Channel Instances Before Compilation for Example 4
Transceiver
Number of
Channels
7
1
and
Figure 3–6
Configuration
Receiver and
Receiver and
Transmitter
Transmitter
show the transceiver instances before and after
Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices
Effective Data Rate: 4.25 Gbps
Input Clock Frequency: 125 MHz
Number of Channels: 7
Effective Data Rate: 4.25 Gbps
Input Clock Frequency: 125 MHz
Number of Channels: 1
Inst0
Inst1
Serial Data Rate (Gbps)
Combining Transceiver Instances in Multiple Transceiver Blocks
4.25
4.25
are identical for inst0 and inst1, the
Table 3–7
Input Reference Clock (MHz)
February 2011 Altera Corporation
with two ALTGX
(same as inst0)
from refclk0
from refclk0
“Multiple
125
125
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