EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 840
EP4SE530H35C2N
Manufacturer Part Number
EP4SE530H35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Manufacturer
Quantity
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Part Number:
EP4SE530H35C2N
Manufacturer:
ALTERA
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4–34
Figure 4–19. Reset Sequence with CDR in Manual Lock Mode
Notes to
(1) For t
(2) For t
(3) For t
Stratix IV Device Handbook Volume 2: Transceivers
Figure 4–19
pll_powerdown
LTR_LTD_Manual
LTD_Manual
duration, refer to the
Reset and Power Down Signals
duration, refer to the
duration, refer to the
Receiver and Transmitter Channel Set-up—Receiver CDR in Manual Lock
Mode
This configuration contains both a transmitter and receiver channel. For Basic (PMA
Direct) drive ×1 mode, with receiver CDR in manual lock mode, use the reset
sequence shown in
mode.
Ouput Status Signals
CDR Control Signals
pll_powerdown[0]
pll_powerdown[3]
rx_analogreset[0]
rx_analogreset[3]
rx_locktorefclk[0]
rx_locktorefclk[3]
rx_dataout[63:0]
rx_locktodata[0]
rx_pll_locked[0]
rx_locktodata[3]
rx_pll_locked[3]
pll_locked
DC and Switching Characteristics for Stratix IV Devices
busy
DC and Switching Characteristics for Stratix IV Devices
DC and Switching Characteristics for Stratix IV Devices
1
t
pll_powerdown (1)
Figure
2
3
4–19. In this example, four channels are configured in this
Minimum of Two Parallel Clock Cycles
4
5
5
t
6
6
LTR_LTD_Manual (2)
Chapter 4: Reset Control and Power Down in Stratix IV Devices
7
7
7
7
t
LTD_Manual (3)
chapter.
chapter.
chapter.
8
valid parallel data into FPGA fabric
PMA Direct Drive Mode Reset Sequences
February 2011 Altera Corporation
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