EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 253
EP4SE530H35C2N
Manufacturer Part Number
EP4SE530H35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4SE530H35C2N
Manufacturer:
ALTERA
Quantity:
147
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- EP4SE230F29C3N PDF datasheet #6
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Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
Table 7–5. DLL Reference Clock Input for EP4SGX70, EP4SGX110, EP4SGX180, and EP4SGX230 Devices in the 780-Pin
FineLine BGA Package
February 2011 Altera Corporation
DLL0
DLL1
DLL2
DLL3
DLL
1
1
(Top/Bottom)
CLK12P
CLK13P
CLK14P
CLK15P
CLK12P
CLK13P
CLK14P
CLK15P
CLK4P
CLK5P
CLK6P
CLK7P
CLK4P
CLK5P
CLK6P
CLK7P
You can only have one memory interface in each I/O sub-bank (such as I/O
sub-banks 1A, 1B, and 1C) when you use leveling delay chains. This is because there
is only one leveling delay chain per I/O sub-bank.
Table 7–4. DLL Location and Supported I/O Banks
The reference clock for each DLL may come from PLL output clocks or any of the two
dedicated clock input pins located in either side of the DLL.
Table 7–17
device family.
When you have a dedicated PLL that only generates the DLL input reference clock, set
the PLL mode to No Compensation to achieve better performance or the Quartus II
software changes it automatically. Because the PLL does not use any other outputs, it
does not need to compensate for any clock paths.
CLKIN
DLL0
DLL1
DLL2
DLL3
Note to
(1) The DLL can access these I/O banks if they are available for memory interfacing.
DLL
Table
lists the available DLL reference clock input resources for the Stratix IV
7–4:
Bottom-right corner
Bottom-left corner
Top-right corner
Top-left corner
Location
(Left/Right)
CLK0P
CLK1P
CLK2P
CLK3P
CLK0P
CLK1P
CLK2P
CLK3P
CLKIN
—
—
(Top/Bottom)
PLL_B1
PLL_B1
PLL_T1
PLL_T1
1A, 1B, 1C, 2A, 2B, 2C, 7A, 7B, 7C, 8A, 8B, 8C
1A, 1B, 1C, 2A, 2B, 2C, 3A, 3B, 3C, 4A, 4B, 4C
3A, 3B, 3C, 4A, 4B, 4C, 5A, 5B, 5C, 6A, 6B, 6C
5A, 5B, 5C, 6A, 6B, 6C, 7A, 7B, 7C, 8A, 8B, 8C
PLL
Accessible I/O Banks
(Left/Right)
PLL_L2
PLL
—
—
—
Stratix IV Device Handbook Volume 1
Table 7–5
(1)
through
(Corner)
PLL
—
—
—
—
7–33
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