EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 731
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EP4SE530H35C2N
Manufacturer Part Number
EP4SE530H35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4SE530H35C2N
Manufacturer:
ALTERA
Quantity:
147
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
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- Download datasheet (32Mb)
Chapter 2: Transceiver Clocking in Stratix IV Devices
FPGA Fabric-Transceiver Interface Clocking
Figure 2–32. Sixteen Identical Channels Across Four Transceiver Blocks for Example 5
February 2011 Altera Corporation
Common Clock Driver Selection Rules
The common clock driver driving the tx_coreclk ports of all identical channels must
have 0 PPM frequency difference with respect to the transmitter phase compensation
FIFO read clocks of these channels. If there is any frequency difference between the
FIFO write clock (tx_coreclk) and the FIFO read clock, the FIFO overflows or
under-runs, resulting in corrupted data transfer between the FPGA fabric and the
transmitter.
Channel [15:12]
Channel [3:0]
Channel [11:8]
and Control
and Control
Channel [7:4]
and Control
and Control
TX Data
TX Data
TX Data
TX Data
Logic
Logic
Logic
Logic
FPGA
Fabric
tx_coreclk[15:12]
tx_coreclk[3:0]
tx_coreclk[11:8]
tx_coreclk[7:4]
Clock Driver
Common
tx_clkout[12]
tx_clkout[8]
tx_clkout[4]
tx_clkout[0]
Transceiver Block
Transceiver Block
Transceiver Block
Transceiver Block
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Stratix IV Device Handbook Volume 2: Transceivers
GXBR
GXBR3
GXBR
GXBR
2
0
1
2–59
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