EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 725
EP4SE530H35C2N
Manufacturer Part Number
EP4SE530H35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4SE530H35C2N
Manufacturer:
ALTERA
Quantity:
147
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Chapter 2: Transceiver Clocking in Stratix IV Devices
FPGA Fabric-Transceiver Interface Clocking
February 2011 Altera Corporation
1
Example 3 assumes channels 0 and 1, driven by CMU0_PLL in a transceiver block, are
identical. Also, channels 2 and 3, driven by CMU1_PLL in the same transceiver block,
are identical. In this case, the Quartus II software automatically drives the write port
of the transmitter phase compensation FIFO in channels 0 and 1 with the
tx_clkout[0] signal. It also drives the write port of the transmitter phase
compensation FIFO in channels 2 and 3 with the tx_clkout[2] signal. Use the
tx_clkout[0] signal to clock the transmitter data and control logic for channels 0
and 1 in the FPGA fabric. Use the tx_clkout[2] signal to clock the transmitter data
and control logic for channels 2 and 3 in the FPGA fabric.
This configuration uses two FPGA global and/or regional clock resources, one for the
tx_clkout[0] signal and the other for the tx_clkout[2] signal.
Example 3: Two Groups of Two Identical Channels in a Transceiver Block
Stratix IV Device Handbook Volume 2: Transceivers
2–53
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