EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 874

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EP4SE530H35C2N

Manufacturer Part Number
EP4SE530H35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
STRATIX® IV Er

Specifications of EP4SE530H35C2N

Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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5–28
Stratix IV Device Handbook Volume 2: Transceivers
1
You can select CMU0 PLL by specifying its identity in the ALTGX MegaWizard Plug-In
Manager. This identification is referred to as the logical tx pll value. This value
provides a logical identification to CMU0 PLL and associates it with a transceiver
channel without requiring the knowledge of its physical location.
In the ALTGX MegaWizard Plug-In Manager, the transmitter PLL configuration set in
the General screen is called the main PLL. When you provide the alternate PLL with a
logical tx pll value (for example, 0), the main PLL automatically takes the
complement value 1. The logical tx pll value for the main PLL is stored along with
the other transceiver channel information in the generated .mif.
The main PLL corresponds to the CMU PLL configuration set in the General screen of
the ALTGX MegaWizard Plug-In Manager. The alternate PLL corresponds to the
CMU PLL configuration set in the Alt PLL screen.
Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Modes Implementation
February 2011 Altera Corporation

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