EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 877
EP4SE530H35C2N
Manufacturer Part Number
EP4SE530H35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4SE530H35C2N
Manufacturer:
ALTERA
Quantity:
147
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Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Modes Implementation
Figure 5–17. Option 1 for Transmitter Core Clocking (Channel and CMU PLL Reconfiguration Mode)
February 2011 Altera Corporation
FPGA Fabric
tx_clkout[0]
Low-speed parallel clock generated by the TX0 local divider (tx_clkout[0])
High-speed serial clock generated by the CMU0 PLL
Figure 5–17
channels of a transceiver block.
■
■
Consider the following scenario:
■
■
■
Option 2 is applicable in this scenario because the design requires all four regular
transceiver channels to be reconfigured to different data rates and functional modes.
Each channel can be reconfigured to a different functional mode using the channel
and CMU PLL reconfiguration mode.
Enable this option if you want the individual transmitter channel tx_clkout
signals to provide the write clock to their respective Transmit Phase Compensation
FIFOs.
This option is typically enabled when each transceiver channel is reconfigured to a
different functional mode using channel reconfiguration.
Four regular transceiver channels configured at 3 Gbps and different functional
modes.
Channel and CMU PLL reconfiguration mode is enabled in the
ALTGX_RECONFIG MegaWizard Plug-In Manager.
You want to reconfigure each of the four regular transceiver channels to different
data rates and different functional modes.
Option 2: Use the Respective Channel Transmitter Core Clocks
shows the sharing of channel 0’s tx_clkout between all four regular
TX0 (3 Gbps/1.5 Gbps)
TX1 (3 Gbps/1.5 Gbps)
TX2 (3 Gbps/1.5 Gbps)
TX3 (3 Gbps/1.5 Gbps)
Transceiver Block
RX3
RX1
RX2
RX0
Stratix IV Device Handbook Volume 2: Transceivers
CMU1 PLL
CMU0 PLL
5–31
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