EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 599
EP4SE530H35C2N
Manufacturer Part Number
EP4SE530H35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
February 2011 Altera Corporation
PCS code groups are sent via PCS ordered sets. PCS ordered sets consist of
combinations of special and data code groups defined as a column of code groups.
These ordered sets are composed of four code groups beginning in lane 0.
lists the defined idle ordered sets (||I||) that are used for the self-managed
properties of XAUI.
Table 1–59. Defined Idle Ordered Set
Stratix IV GX and GT transceivers configured in XAUI mode provide the following
protocol features:
■
■
■
■
■
■
XGMII-to-PCS code conversion at the transmitter
PCS-to-XGMII code conversion at the receiver
8B/10B encoding and decoding
IEEE P802.3ae-compliant synchronization state machine
±100 PPM clock rate compensation
Channel deskew of four lanes of the XAUI link
Code
||R||
||K||
||A||
||I||
Synchronization column
Align column
Skip column
Ordered Set
Idle
Code Groups
Number of
4
4
4
Stratix IV Device Handbook Volume 2: Transceivers
/K28.5/K28.5/K28.5/K28.5/
/K28.0/K28.0/K28.0/K28.0/
/K28.3/K28.3/K28.3/K28.3/
Substitute for XGMII Idle
Encoding
Table 1–59
1–155
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