EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 928
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EP4SE530H35C2N
Manufacturer Part Number
EP4SE530H35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
EP4SE530H35C2N
Manufacturer:
ALTERA
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- EP4SGX110DF29C3N PDF datasheet
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- EP4SE230F29C3N PDF datasheet #6
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5–82
Table 5–16. Dynamic Reconfiguration Controller Port List (ALTGX_RECONFIG Instance) (Part 7 of 13)
Stratix IV Device Handbook Volume 2: Transceivers
tx_preemp_0t[4:0]
tx_preemp_1t[4:0]
Port Name
(1)
(1)
Output
Input/
Input
Input
This is an optional pre-emphasis control for pre-tap for the transmit
buffer. Depending on what value you set at this input, the controller
dynamically writes the value to the pre-emphasis control register of
the transmit buffer. This signal controls both pre-emphasis positive
and its inversion.
The width of this signal is fixed to 5 bits if you enable either the Use
'logical_channel_address' port for Analog controls
reconfiguration option or the Use same control signal for all the
channels option in the Analog controls screen. Otherwise, the
width of this signal is 5 bits per channel.
For more information, refer to
Controls” on page
The following values are the legal settings allowed for this signal:
0 represents 0
1-15 represents -15 to -1
16 represents 0
17 - 31 represents 1 to 15
In the PCIe configuration, set tx_preemp_0t[4:0] to 5'b00000
when you do a rate switch from Gen 1 mode to Gen 2 mode. This is
to ensure that tx_preemp_0t[4:0] does not add to the signal
boost when tx_pipemargin and tx_pipedeemph take affect in
PCIe Gen 2 mode.
For more information, refer to the “Programmable Pre-Emphasis”
section of the
This is an optional pre-emphasis write control for the first post-tap
for the transmit buffer. Depending on what value you set at this
input, the controller dynamically writes the value to the first
post-tap control register of the transmit buffer.
The width of this signal is fixed to 5 bits if you enable either the Use
'logical_channel_address' port for Analog controls
reconfiguration option or the Use same control signal for all the
channels option in the Analog controls screen. Otherwise, the
width of this signal is 5 bits per channel.
For more information, refer to
Controls” on page 5–13
section of the
Transceiver Architecture in Stratix IV Devices
Transceiver Architecture in Stratix IV Devices
Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
5–13.
and the “Programmable Pre-Emphasis”
Description
Dynamic Reconfiguration Controller Port List
“Dynamically Reconfiguring PMA
“Dynamically Reconfiguring PMA
February 2011 Altera Corporation
(Note
3),
chapter.
chapter.
(4)
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