EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 800
EP4SE530H35C2N
Manufacturer Part Number
EP4SE530H35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4SE530H35C2N
Manufacturer:
ALTERA
Quantity:
147
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3–46
Figure 3–23. Three Transceiver Block Configuration for Example 13
Notes to
(1) CMU channels are used for clock generation.
(2) The red lines represent the ×N top clock line, the blue lines represent the ×1 clock line, the black lines represent ×N bottom clock, the green lines
Stratix IV Device Handbook Volume 2: Transceivers
represents the CMU1 channel, and the brown lines represent the CMU0 channel.
Figure
3–23:
QL2
QL0
QL1
Figure 3–23
TX2: four data rates
TX0: four data rates
shows the configuration for Example 13.
TX0: SONET OC48
TX2: SONET OC48
(SONET OC 48) (1)
TX1: four data rates
TX3: four data rates
CMU0 Channel
TX0: GIGE
TX2: GIGE
CMU0 Channel
CMU0 Channel
TX3: SONET OC48
CMU1 Channel
(GIGE) (1)
TX1: GIGE
TX1: SONET OC48
TX3: GIGE
(FC 2G) (1)
(OTU1) (1)
Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices
Combination Requirements When You Enable Channel Reconfiguration
x1 Clock Line (2)
x1 Clock Line (2)
xN_Top Clock Li
February 2011 Altera Corporation
Clock Line (2
xN_Bottom
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