EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 611

• Manufacturer Part Number: EP4SE530H35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–133. GIGE Mode Datapath
Table 1–62. Transceiver Datapath Clock Frequencies in GIGE Mode
February 2011 Altera Corporation
Functional Mode
GIGE
rx_coreclk[0]
tx_coreclk[0]
FPGA
Fabric
FPGA
Fabric-Transceiver
Interface Clock
GIGE Mode Datapath
Figure 1–133
mode.
Table 1–62
8B/10B Encoder
In GIGE mode, the 8B/10B encoder clocks in 8-bit data and 1-bit control identifiers
from the transmitter phase compensation FIFO and generates 10-bit encoded data.
The 10-bit encoded data is fed to the serializer. For more information about 8B/10B
encoder functionality, refer to
GIGE Protocol—Ordered Sets and Special Code Groups
Table 1–63
specification.
Table 1–63. GIGE Ordered Sets (Part 1 of 2)
Code
/C1/
/C2/
/C/
Compensation
1.25 Gbps
Data Rate
tx_clkout[0]
RX Phase
FIFO
Compensation
wrclk rdclk
TX Phase
lists the transceiver datapath clock frequencies in GIGE functional mode.
lists ordered sets and special code groups specified in the IEEE 802.3
FIFO
shows the transceiver datapath when configured in GIGE functional
Configuration 1
Configuration 2
8B/10B
Decoder
Configuration
8B/10B
Decoder
Ordered Set
High-Speed Serial
Clock Frequency
625 MHz
Match
FIFO
Rate
“8B/10B Encoder” on page
Transmitter Channel PCS
Low-Speed Parallel Clock
Low-Speed Parallel Clock
Receiver Channel PCS
Number of Code
Parallel Recovered
8B/10B
Encoder
Parallel Recovered Clock
Parallel Clock
Groups
Low-Speed
Frequency
Clock and
Aligner
Word
125 MHz
—
4
4
Stratix IV Device Handbook Volume 2: Transceivers
Serializer
Receiver Channel PMA
Serializer
Transmitter Channel PMA
De-
De-
Serializer
Clock Divider
/K28.5/D21.5/Config_Reg
/K28.5/D2.2/Config_Reg
1–23.
Local
Interface Clock Frequency
Alternating /C1/ and /C2/
FPGA Fabric-Transceiver
CDR
High-Speed Serial Clock
Encoding
125 MHz
(1)
(1)
1–167