EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 511

• Manufacturer Part Number: EP4SE530H35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–53. Manual Alignment Mode Word Aligner in 16-Bit PMA-PCS Interface Modes
February 2011 Altera Corporation
rx_patterndetect[1:0]
rx_enapatternalign
rx_syncstatus[1:0]
Word aligner operation is controlled by the input signal rx_enapatternalign and is
edge-sensitive to the rx_enapatternalign signal. A rising edge on the
rx_enapatternalign signal triggers the word aligner to look for the word alignment
pattern in the received data stream. The word aligner aligns the 16-bit word boundary
to the first word alignment pattern received after the rising edge on the
rx_enapatternalign signal. Any word alignment pattern received thereafter in a
different word boundary does not cause the word aligner to re-align to this new word
boundary. If another word re-alignment is required, you must de-assert and re-assert
the rx_enapatternalign signal to create a rising edge on this signal.
Two status signals, rx_syncstatus and rx_patterndetect, with the same latency as
the datapath, are forwarded to the FPGA fabric to indicate word aligner status.
After receiving the first word alignment pattern, the rx_patterndetect signal is
driven high for one parallel clock cycle synchronous to the data that matches the
MSByte of the word alignment pattern. Any word alignment pattern received
thereafter in the same word boundary causes rx_patterndetect to go high for one
parallel clock cycle.
After receiving the first word alignment pattern, the rx_syncstatus signal is
constantly driven high until the word aligner sees another rising edge on the
rx_enapatternalign signal. The rising edge on the rx_enapatternalign signal
re-triggers the word alignment operation.
Figure 1–53
PMA-PCS interface mode. In this example, a 16'hF628 is specified as the word
alignment pattern. The word aligner aligns to the 16'hF628 pattern received in cycle n
after de-assertion of rx_digitalreset. The rx_patterndetect[1] signal is driven
high for one parallel clock cycle. The rx_syncstatus[1] signal is driven high
constantly until cycle n + 2, after which it is driven low because of the rising edge on
the rx_enapatternalign signal that re-triggers the word aligner operation. The word
aligner receives the word alignment pattern again in cycle n + 4, causing the
rx_patterndetect[1] signal to be driven high for one parallel clock cycle and the
rx_syncstatus[1] signal to be driven high constantly.
rx_digitalreset
rx_dataout
shows the manual alignment mode word aligner operation in 16-bit
00
00
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F628
10
10
n
11
n + 1
xxxx
n + 2
xxxx
00
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n + 3
Stratix IV Device Handbook Volume 2: Transceivers
F628
n + 4
10
10
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11
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