EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 306
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EP4SE530H35C2N
Manufacturer Part Number
EP4SE530H35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4SE530H35C2N
Manufacturer:
ALTERA
Quantity:
147
- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
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8–28
Example 8–1. Generating Three Output Clocks Using an ALTPLL Megafunction
LVDS data rate = 1 Gbps; serialization factor = 10; input reference clock = 100 MHz
The following settings are used when generating the three output clocks using an ALTPLL megafunction.
The serial clock must be 1000 MHz and the parallel clock must be 100 MHz (serial clock divided by the
serialization factor):
■
■
■
Stratix IV Device Handbook Volume 1
c0
■
■
■
c1
■
■
■
c2
■
■
■
Frequency = 1000 MHz (multiplication factor = 10 and division factor = 1)
Phase shift = –180° with respect to the voltage-controlled oscillator (VCO) clock
Duty cycle = 50%
Frequency = (1000/10) = 100 MHz (multiplication factor = 1 and division factor = 1)
Phase shift = (10 - 2) × 360/10 = 288° [(deserialization factor - 2)/deserialization factor] × 360°
Duty cycle = (100/10) = 10% (100 divided by the serialization factor)
Frequency = (1000/10) = 100 MHz (multiplication factor = 1 and division factor = 1)
Phase shift = (–180/10) = –18° (c0 phase shift divided by the serialization factor)
Duty cycle = 50%
Example 8–1
megafunction.
shows how to generate three output clocks using an ALTPLL
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
LVDS Interface with the Use External PLL Option Enabled
February 2011 Altera Corporation
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