PNX1702EH/G,557 NXP Semiconductors, PNX1702EH/G,557 Datasheet - Page 135

• Manufacturer Part Number: PNX1702EH/G,557
• Description: IC MEDIA PROC 500MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1702EH/G,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Ram Size: 208K x 8
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.33 V ~ 1.47 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-HBGA
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 935281647557; PNX1702EH/G; PNX1702EH/G

Philips Semiconductors
Volume 1 of 1
Table 8: Global Registers
8. Miscellaneous
PNX17XX_SER_1
Preliminary data sheet
Bit
Symbol
…Continued
[8-1]
Several other system MMIO registers are described in the following paragraphs and
detailed in the next
•
•
•
•
By default PCI_INTA_N is an input/output pin used in open drain mode for the
PCI bus. When a host CPU wants to assert an interrupt to the TM5250 it asserts
the PCI_INTA_N low. Similarly if TM5250 wants to notify a host CPU of an
interrupt it can assert low the PCI_INTA_N pin by programming the PCI_INTA
MMIO register.
The 8 SCRATCH MMIO registers are mainly used for debug purpose. Since they
are not reset by the external POR_IN_N or RESET_IN_N signals they can be
used for post-mortem system crash to retain some critical or debug values.
Event timestamping for the SPDI interface comes with a diversity of
requirements. To keep PNX17xx Series as a programmable system, a system
multiplexer is implemented to select which event or signal to timestamp. The
multiplexer is controlled by the SPDI_MUX_SEL MMIO register. The different
selectable signals coming from the SPDI module are displayed in
The SPARE_CTRL MMIO register is reserved for future usage.
Acces
s
Note: *When the LCD IF is enabled, VDO_MODE[2:0] is forced to “000”.
Value
Rev. 1 — 17 March 2006
Section
Description
011*:
FGPO_DATA[8:0]
FGPO_START/REC_START -> VDO_D[32]
FGPO_STOP/BUF_START
FGPO_CLK
100*:
FGPO_DATA[4:0]
FGPO_START/REC_START -> VDO_D[32]
FGPO_STOP/BUF_START
FGPO_CLK
101*:
No FGPO-to-VDO mapping.
110*:
FGPO_DATA[23:0]
FGPO_START/REC_START -> VDO_D[32]
FGPO_STOP/BUF_START
FGPO_CLK
111*:
FGPO_DATA[31:0]
FGPO_START/REC_START -> VDO_D[32]
FGPO_STOP/BUF_START
FGPO_CLK
8.1:
Chapter 3: System On Chip Resources
-> VDO_CLK2
-> VDO_CLK2
-> VDO_CLK2
-> VDO_CLK2
-> VDO_D[33]
-> VDO_D[33]
-> VDO_D[33]
-> VDO_D[33]
-> VDO_D[8:0]
-> VDO_D[4:0]
-> VDO_D[23:0]
-> VDO_D[31:0]
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
Section
8.1.
3-26