PNX1702EH/G,557 NXP Semiconductors, PNX1702EH/G,557 Datasheet - Page 265
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PNX1702EH/G,557
Manufacturer Part Number
PNX1702EH/G,557
Description
IC MEDIA PROC 500MHZ 456-BGA
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1702EHG557.pdf
(832 pages)
Specifications of PNX1702EH/G,557
Applications
Multimedia
Core Processor
TriMedia
Controller Series
Nexperia
Ram Size
208K x 8
Interface
I²C, 2-Wire Serial
Number Of I /o
61
Voltage - Supply
1.33 V ~ 1.47 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
456-HBGA
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Type
-
Lead Free Status / Rohs Status
Compliant
Other names
935281647557
PNX1702EH/G
PNX1702EH/G
PNX1702EH/G
PNX1702EH/G
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Philips Semiconductors
Volume 1 of 1
Table 9: Registers Description
PNX17XX_SER_1
Preliminary data sheet
Bit
5
4
3
2
1
0
Offset 0x04 0FE8
31:27
26
25
24
23
22
21
20
19
18
17
16
15
14
13:12
11
10
9
8
7
6
5
4
3
2
1
0
Offset 0x04 0FEC
31:27
26
Symbol
en_int_pci_mstr_parity
err
en_int_pci_parity
en_int_sig_serr
en_int_pci_r_mabort
en_int_pci_r_tabort
en_int_pci_s_tabort
Reserved
clr_pcii_wr_err
clr_pcii_rd_err
clr_xio_wr_err
clr_xio_rd_err
clr_pcir_wr_err
clr_pcir_rd_err
clr_pwrstate_chg
Reserved
clr_pci2_wr_err
clr_pci2_rd_err
clr_pci1_wr_err
clr_pci1_rd_err
clr_pci_xio_ack_done
Reserved
clr_serr_seen
Reserved
clr_pci_err
clr_base10_subword
clr_base14_subword
clr_base18_subword
clr_pci_mstr_parity_err
clr_pci_parity
clr_sig_serr
clr_pci_r_mabort
clr_pci_r_tabort
clr_pci_s_tabort
Reserved
set_pcii_wr_err
PCI Interrupt Clear
PCI Interrupt Set
Acces
s
R/W
R/W
R/W
R/W
R/W
R/W
R
W
W
W
W
W
W
W
R
W
W
W
W
W
R
W
R
W
W
W
W
W
W
W
W
W
W
R
W
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Rev. 1 — 17 March 2006
Description
Enable interrupt on PCI Master Parity Error
Enable interrupt on PCI Parity Error Status
Enable interrupt on System Error Status
Enable interrupt on PCI Received Master Abort Status
Enable interrupt on PCI Received Target Abort Status
Enable interrupt on PCI Signaled Target Abort Status
Clear PCI DTL initiator write error flag
Clear PCI DTL initiator read error flag
Clear XIO DTL target write error flag
Clear XIO DTL target read error flag
Clear mmio register DTL target write error flag
Clear mmio register DTL target read error
Clear power state change register flag
Clear PCI2 DTL target write error flag
Clear PCI2 DTL target read error flag
Clear PCI1 DTL target write error flag
Clear PCI1 DTL target read error flag
Clear pci_xio_ack done flag
Clear serr_seen flag
Clear pci_err flag
Clear Subword Attempt to Base10 Error Status
Clear Subword Attempt to Base14 Error Status
Clear Subword Attempt to Base18 Error Status
Clear PCI Master Parity Error
Clear PCI Parity Error Status
Clear System Error Status
Clear PCI Received Master Abort Status
Clear PCI Received Target Abort Status
Clear PCI Signaled Target Abort Status
Set PCI DTL initiator write error flag
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Chapter 7: PCI-XIO Module
PNX17xx Series
7-44
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