PNX1702EH/G,557 NXP Semiconductors, PNX1702EH/G,557 Datasheet - Page 741
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PNX1702EH/G,557
Manufacturer Part Number
PNX1702EH/G,557
Description
IC MEDIA PROC 500MHZ 456-BGA
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1702EHG557.pdf
(832 pages)
Specifications of PNX1702EH/G,557
Applications
Multimedia
Core Processor
TriMedia
Controller Series
Nexperia
Ram Size
208K x 8
Interface
I²C, 2-Wire Serial
Number Of I /o
61
Voltage - Supply
1.33 V ~ 1.47 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
456-HBGA
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Type
-
Lead Free Status / Rohs Status
Compliant
Other names
935281647557
PNX1702EH/G
PNX1702EH/G
PNX1702EH/G
PNX1702EH/G
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Philips Semiconductors
Volume 1 of 1
PNX17XX_SER_1
Preliminary data sheet
5.14.1 Enabling and Disabling Reception
5.14 Enabling and Disabling Receive and Transmit
When a magic packet is detected, apart from the WakeupInt bit in the IntStatus
register, the MagicPacketWoL bit is set in the RxFilterWoLStatus register. Software
can reset the bit by writing a 1 to the corresponding bit of the RxFilterWoLClear
register.
Magic Packet WoL Example
An example of a Magic Packet with station address 11h 22h 33h 44h 55h 66h is as
follows. MISC indicates miscellaneous additional data bytes in the packet.
DESTINATION SOURCE MISC FF FF FF FF FF
FF 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44
55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33
44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22
33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11
22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66
11 22 33 44 55 66 11 22 33 44 55 66 MISC CRC
After reset, the receive function of the LAN100 is disabled. The receive function can
be enabled by the device driver by setting the RxEnable bit in the Command register
and the RECEIVE_ENABLE bit in the MAC1 configuration register of the LAN100.
The status of the Receive Datapath can be monitored by the device driver by reading
the RxStatus bit of the Status register. Figure 14 illustrates the finite state machine
(FSM) for generating the RxStatus bit.
Figure 14: Receive Active/Inactive state machine
RxEnable
Reset
Rev. 1 — 17 March 2006
Chapter 23: LAN100 — Ethernet Media Access Controller
RxStatus=1
RxStatus=0
INACTIVE
ACTIVE
!RxEnable && not busy receiving
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
23-68
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