PNX1702EH/G,557 NXP Semiconductors, PNX1702EH/G,557 Datasheet - Page 745

• Manufacturer Part Number: PNX1702EH/G,557
• Description: IC MEDIA PROC 500MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1702EH/G,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Ram Size: 208K x 8
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.33 V ~ 1.47 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-HBGA
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 935281647557; PNX1702EH/G; PNX1702EH/G

Philips Semiconductors
Volume 1 of 1
PNX17XX_SER_1
Preliminary data sheet
All the above reset bits must be cleared by software.
The RESET_PERMII bit in the SUPP register allows soft resetting of the RMII logic.
The reset must be cleared by software.
The Command register (see
To do a full soft reset of the LAN100 device driver, software must:
To reset just the Transmit Datapath, the device driver software must:
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RESET_PEMCS_Rx: Setting this bit will reset the MAC Control Sublayer (the
pause frame logic) and the Receive function of the MII Interface. The value after a
hard reset is 0.
RESET_PERFUN: Setting this bit will reset the receive function in the MII
Interface. The value after a hard reset is 0.
RESET_PEMCS_Tx: Setting this bit will reset the MAC Control Sublayer (pause
frame logic) and the Transmit function of the MII Interface. The value after a hard
reset is 0.
RESET_PETFUN: Setting this bit will reset the transmit function of the MII
Interface. The value after a hard reset is 0.
TxReset: Writing a 1 to the TxReset bit will reset the Transmit Datapath,
excluding the MII Interface portions, including all (read-only) registers in the
Transmit Datapath, and also the TxProduceIndex register in the host registers
module. Soft resetting the Transmit Datapath will abort all memory operations of
the Transmit Datapath. The reset bit will be cleared automatically by the LAN100.
Soft resetting the Tx datapath will clear the TxStatus and TxRtStatus bits in the
Status register.
RxReset: Writing a 1 to the RxReset bit will reset the Receive Datapath,
excluding the MII Interface portions, including all (read-only) registers in the
Receive Datapath, and also the RxConsumeIndex register in the host registers
module. Soft resetting the Receive Datapath will abort all memory operations of
the Receive Datapath. The reset bit will be cleared automatically by the LAN100.
Soft resetting the Rx datapath will clear the RxStatus bit in the Status register.
RegReset: Writing a 1 to the RegReset bit resets all of the datapaths and
LAN100 registers, but not the registers in the MII Interface. Soft resetting the
registers aborts all memory operations of the Transmit and Receive datapaths.
The reset bit will be cleared automatically by the LAN100.
Set the SOFT_RESET bit in the MAC1 register to 1
Set the RegReset bit in the Command register (this bit clears automatically)
Reinitialize the MII Interface registers (0x000-0x0FC)
Clear the SOFT_RESET bit in the MAC1 register to 0.
Set the RESET_PEMCS_Tx bit in the MAC1 register to 1
Rev. 1 — 17 March 2006
Chapter 23: LAN100 — Ethernet Media Access Controller
Table
2) has three different reset bits:
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
23-72