PNX1702EH/G,557 NXP Semiconductors, PNX1702EH/G,557 Datasheet - Page 791
![no-image](/images/manufacturer_photos/0/4/487/nxp_semiconductors_sml.jpg)
PNX1702EH/G,557
Manufacturer Part Number
PNX1702EH/G,557
Description
IC MEDIA PROC 500MHZ 456-BGA
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1702EHG557.pdf
(832 pages)
Specifications of PNX1702EH/G,557
Applications
Multimedia
Core Processor
TriMedia
Controller Series
Nexperia
Ram Size
208K x 8
Interface
I²C, 2-Wire Serial
Number Of I /o
61
Voltage - Supply
1.33 V ~ 1.47 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
456-HBGA
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Type
-
Lead Free Status / Rohs Status
Compliant
Other names
935281647557
PNX1702EH/G
PNX1702EH/G
PNX1702EH/G
PNX1702EH/G
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Philips Semiconductors
Volume 1 of 1
PNX17XX_SER_1
Preliminary data sheet
1.1.5 SDRAM Controller
This powerdown state can be initiated by an external host processor by writing to bit
TM32_CONTROL.TM_PWRDWN_REQ, see
The TM5250 only exits this mode when this bit is de-asserted. At this point in time the
TM5250 clock may be removed by the host.
The second method to shutdown the TM5250 clock as well as the MMIO clock is to
follow the procedure defined in
page
master of the system.
Power consumption of the MMI is lowest when it is halted. There are two different
ways to achieve halting the MMI:
Remark: Before halting the MMI, make sure that there are no pending memory
transactions.
MMIO Directed Halt
The HALT bit of MMIO register IP_2031_CTL can be written with a ‘1’ to indicate a
request for halting. Write a ‘0’ to this bit to indicate a request for taking the DDR
controller out of halt mode.
Remark: It is recommended that putting the MMI in MMIO direct-halt mode (with
MMIO registers) before reprogramming the configuration and timing registers in MMI
so that the on-going transactions are not effected. When MMIO registers DDR_MR
and DDR_EMR are reprogrammed, a start action has to be performed (after the MMI
is unhalted), for the new DDR values to take effect.
Auto Halt
The MMI can be programmed such that it goes into halt mode when it has observed a
certain period of inactivity. This is accomplished by programming the MMIO registers
AUTO_HAL_LIMIT and IP_2031_CTL. The MMI will exit the halt mode automatically
when a new MTL memory request is presented to one of its input ports. The MTL
clock and DCS clock cannot be turned off to operate in this mode.
Remark: This modes introduces extra latency on memory transactions and it is not a
recommended operating mode.
•
•
Writing the halt register field of a software programmable MMIO register.
Programming the MMI to go into halt mode automatically after a certain period of
inactivity.
27-1. This is solution for standalone systems where PNX17xx Series is the
Rev. 1 — 17 March 2006
Chapter 5 The Clock Module Section 27 on
Chapter 3 System On Chip
Chapter 27: Power Management
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
Resources.
27-3
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