PNX1702EH/G,557 NXP Semiconductors, PNX1702EH/G,557 Datasheet - Page 587
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PNX1702EH/G,557
Manufacturer Part Number
PNX1702EH/G,557
Description
IC MEDIA PROC 500MHZ 456-BGA
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1702EHG557.pdf
(832 pages)
Specifications of PNX1702EH/G,557
Applications
Multimedia
Core Processor
TriMedia
Controller Series
Nexperia
Ram Size
208K x 8
Interface
I²C, 2-Wire Serial
Number Of I /o
61
Voltage - Supply
1.33 V ~ 1.47 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
456-HBGA
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Type
-
Lead Free Status / Rohs Status
Compliant
Other names
935281647557
PNX1702EH/G
PNX1702EH/G
PNX1702EH/G
PNX1702EH/G
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Philips Semiconductors
Volume 1 of 1
PNX17XX_SER_1
Preliminary data sheet
Figure 3:
Figure 4:
8/8/8/8
8/8/8/8
MBS Horizontal Processing Pipeline
MBS Vertical Processing Pipeline
7 Lines in Total
Deinterlacing
2.2.1 Horizontal Processing Pipeline
2.2.2 Vertical Processing Pipeline
(4:2:2 ->4:4:4)
IFF
Figure 2
pipelines — Vertical processing Pipeline and Horizontal Processing Pipeline — that,
for most applications, can be used in any order; for 3-field majority selection,
however, vertical processing has to be done first.
Figure 3
for chroma up-sampling, horizontal scaling, color-space conversion, and chroma
down-sampling. Note that only one of either horizontal scaling or color-space
conversion can be done at any one time., i.e., these operations are mutually
exclusive. The scaler coefficients are the same for both chroma and luma.
Figure 4
interlacing, EDDI-based post-processing, and vertical scaling (that also allows 4:2:0
<-> 4:2:2 sampling conversions for chroma). De-interlacing for luma samples uses
majority-select or median filtering; de-interlacing for chroma always uses median
8/8/8/
8/8
shows the top-level structure of MBS. There are two independent processing
elaborates on the Horizontal Processing Pipeline (HPP). HPP is responsible
shows the Vertical Processing Pipeline (VPP). VPP comprises de-
8/8/8/8
Rev. 1 — 17 March 2006
EDDI
Color Space
Conversion
Pipeline or
Horizontal
Scaling
8/8/8/8
8/8
8/8/8/8
Chapter 19: Memory Based Scaler
8/8/8/8
(4:4:4 ->4:2:2)
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
12 Lines in Total
DFF
PNX17xx Series
<->4:2:2)
Pipeline
Vertical
Scaling
(4:2:0
8/8/8/8
8/8/8/8
19-4
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