PNX1702EH/G,557 NXP Semiconductors, PNX1702EH/G,557 Datasheet - Page 160
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PNX1702EH/G,557
Manufacturer Part Number
PNX1702EH/G,557
Description
IC MEDIA PROC 500MHZ 456-BGA
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1702EHG557.pdf
(832 pages)
Specifications of PNX1702EH/G,557
Applications
Multimedia
Core Processor
TriMedia
Controller Series
Nexperia
Ram Size
208K x 8
Interface
I²C, 2-Wire Serial
Number Of I /o
61
Voltage - Supply
1.33 V ~ 1.47 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
456-HBGA
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Type
-
Lead Free Status / Rohs Status
Compliant
Other names
935281647557
PNX1702EH/G
PNX1702EH/G
PNX1702EH/G
PNX1702EH/G
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Philips Semiconductors
Volume 1 of 1
Table 2: Current Adjustment Values Based on N
Table 3: PLL Setting Examples
PNX17XX_SER_1
Preliminary data sheet
30-37 38-46 47-54 55-63 64-72 73-82 83-89 90-97 98-107 108-116 117-125 126-133 134-142 143-151 152-160 161-180
0xF
F
133.07 MHz 266.14 MHz 27 MHz CRYSTAL
181.29 MHz 362.57 MHz 27 MHz CRYSTAL
144.5 MHz
166.5 MHz
199.8 MHz
399.6 MHz
450.0 MHz
499.5 MHz
out
27 MHz
54 MHz
65 MHz
81 MHz
0xE
0xD
F
577.8 MHz
399.6 MHz
399.6 MHz
450.0 MHz
499.5 MHz
vco
216 MHz
432 MHz
520 MHz
324 MHz
333 MHz
0xC
0xB
F
27 MHz CRYSTAL
27 MHz CRYSTAL
27 MHz CRYSTAL
27 MHz CRYSTAL
27 MHz CRYSTAL
in
27.012987 MHz
27.009345 MHz
PLL Settings
An easy way to determine the N over M ratio is to meet the PLL limitations seen
above and solve the following equation:
PLL Setting Examples
Table 1
PLL2 (for the DDR) has the P parameter wired to ‘1’.
---- -
M
N
•
•
0xA
=
27 MHz
27 MHz
27 MHz
Run the VCO as high as possible, therefore for low output frequencies chose high
P values
Ensure
DDS1
DDS1
DDS1
DDS1
DDS1
F
---------- -
F
vco
in
presents some other typical examples to set the PLL N, M and P parameters.
0x9
30 N 180
0x8
M
Rev. 1 — 17 March 2006
4
3
4
3
3
7
3
7
5
5
3
2
0x7
and track N with the following current adjustment values:
N
0x4D
0x20
0x30
0x24
0x24
0x45
0x25
0x5E
0x4A
0x4A
0x32
0x25
0x6
P
n/a
n/a
n/a
n/a
3
3
3
2
2
0
0
0
0x5
ADJ
0xD
0xA
0xB
0xA
0xA
0xD
0xF
0xF
0xF
0xF
0x8
0xF
0x4
Destination Examples
QVCP from DDS1
50% duty cycle recommended
QVCP from DDS1
50% duty cycle recommended
QVCP from DDS1
50% duty cycle recommended
QVCP from DDS1
50% duty cycle recommended
QVCP from DDS1
50% duty cycle recommended
DDR266, i.e. <= 133.333333 MHz MM_CK
DDR333, i.e. <= 166.666666 MHz MM_CK
DDR366, i.e. <= 181.818181 MHz MM_CK
DDR400, i.e. <= 200.000000 MHz MM_CK
400 MHz TM5250
450 MHz TM5250
500 MHz TM5250
0x3
Chapter 5: The Clock Module
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
0x2
0x1
0x0
(6)
5-9
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