PNX1702EH/G,557 NXP Semiconductors, PNX1702EH/G,557 Datasheet - Page 256
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PNX1702EH/G,557
Manufacturer Part Number
PNX1702EH/G,557
Description
IC MEDIA PROC 500MHZ 456-BGA
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1702EHG557.pdf
(832 pages)
Specifications of PNX1702EH/G,557
Applications
Multimedia
Core Processor
TriMedia
Controller Series
Nexperia
Ram Size
208K x 8
Interface
I²C, 2-Wire Serial
Number Of I /o
61
Voltage - Supply
1.33 V ~ 1.47 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
456-HBGA
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Type
-
Lead Free Status / Rohs Status
Compliant
Other names
935281647557
PNX1702EH/G
PNX1702EH/G
PNX1702EH/G
PNX1702EH/G
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Philips Semiconductors
Volume 1 of 1
Table 9: Registers Description
PNX17XX_SER_1
Preliminary data sheet
Bit
13:9
8:5
4:3
2:1
0
Offset 0x04 0820
31:0
Offset 0x04 0824
31:0
Offset 0x04 0828
31:0
Offset 0x04 082C
This register controls the type of access to XIO and provides status.
31:10
9
8
7
6
5
Symbol
sel2_wait
sel2_offset
sel2_type
sel2_siz
en_sel2
gpxio_addr
gpxio_wdata
gpxio_rdata
Reserved
gpxio_cyc_pending
gpxio_done
clr_gpxio_done
gpxio_init
Reserved
GPXIO_address
GPXIO_write_data
GPXIO_read_data
GPXIO_ctrl
Acces
s
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
W
R/W
R
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
Rev. 1 — 17 March 2006
Description
68360: DS time low if using fixed timing.
NOR: OEN time low if not using ACK.
NAND: Delay between address and data phase if not using ACK,
delay until monitoring ACK.
IDE: Not used.
Address offset form start address of XIO aperture, in 8M
increments. This field must be naturally aligned with the size of the
profile.
Sel2 is configured as:
Amount of address space allocated to Sel2 [25,2:1]:
000 = 8M
001 = 16M
010 = 32M
011 = 64M
100 = 128M
Enable sel2 profile.
General Purpose XIO cycle address. This register sets the address
for an indirect read or write to/from XIO address space. Only 4 byte
writes are allowed in this register. The values programmed for bits 0
and 1 are not used by the XIO module. Refer to gpxio_ben.
General Purpose XIO cycle data. This register is programmed with
data for a write cycle.
General Purpose XIO cycle data. This register contains the data of
a read cycle after completion.
1 = GPXIO transaction on XIO is pending.
0 = GPXIO has completed or not yet started.
General Purpose XIO cycle complete. This bit is cleared by writing 1
to bit 6 or 7. It will also be cleared by writing to the GPXIO interrupt
clear register.
1 = Clear “gpxio_done.”
1 = Initiate a transaction on XIO. The type of transaction will match
the profile of the selected aperture. This bit gets cleared if the cycle
has been initiated. This bit clears bit 8 if set.
00 = 68360 type device
01 = NOR Flash
10 = NAND-Flash
11 = IDE
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Chapter 7: PCI-XIO Module
PNX17xx Series
7-35
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